Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 448 Preliminary © 2007 Microchip Technology Inc.
FIGURE 27-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 27-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 27-4 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 27-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 T
CKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns