Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 439
PIC18F2585/2680/4585/4680
FIGURE 27-11: PARALLEL SLAVE PORT TIMING (PIC18F4585/4680)
TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4585/4680)
Note: Refer to Figure 27-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 T
DTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns
63 T
WRH2DTIWR ↑ or CS ↑ to Data–In Invalid
(hold time)
PIC18FXXXX 20 — ns
PIC18LFXXXX 35 — ns VDD = 2.0V
64 T
RDL2DTVRD ↓ and CS ↓ to Data–Out Valid — 80 ns
65 T
RDH2DTIRD ↑ or CS ↓ to Data–Out Invalid 10 30 ns
66 T
IBFINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ —3 TCY