Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 282 Preliminary © 2007 Microchip Technology Inc.
23.2.2 DEDICATED CAN TRANSMIT
BUFFER REGISTERS
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 23-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]
Mode 0
R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
TXBIF TXABT
(1)
TXLARB
(1)
TXERR
(1)
TXREQ
(2)
— TXPRI1
(3)
TXPRI0
(3)
Mode 1, 2
R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
TXBIF TXABT
(1)
TXLARB
(1)
TXERR
(1)
TXREQ
(2)
— TXPRI1
(3)
TXPRI0
(3)
bit 7 bit 0
bit 7 TXBIF: Transmit Buffer Interrupt Flag bit
1 = Transmit buffer has completed transmission of message and may be reloaded
0 = Transmit buffer has not completed transmission of a message
bit 6 TXABT: Transmission Aborted Status bit
(1)
1 = Message was aborted
0 = Message was not aborted
bit 5 TXLARB: Transmission Lost Arbitration Status bit
(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERR: Transmission Error Detected Status bit
(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQ: Transmit Request Status bit
(2)
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
bit 2 Unimplemented: Read as ‘0’
bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits
(3)
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note 1: This bit is automatically cleared when TXREQ is set.
2: While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in
software while the bit is set will request a message abort.
3: These bits define the order in which transmit buffers will be transferred. They do not alter
the CAN message identifier.
Legend:
C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown