Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 281
PIC18F2585/2680/4585/4680
REGISTER 23-4: COMSTAT: COMMUNICATION STATUS REGISTER
Mode 0
R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0
RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN
Mode 1
R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0
— RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN
Mode 2
R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0
FIFOEMPTY
RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN
bit 7 bit 0
bit 7 Mode 0:
RXB0OVFL: Receive Buffer 0 Overflow bit
1 = Receive Buffer 0 overflowed
0 = Receive Buffer 0 has not overflowed
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FIFOEMPTY: FIFO Not Empty bit
1 = Receive FIFO is not empty
0 = Receive FIFO is empty
bit 6 Mode 0:
RXB1OVFL: Receive Buffer 1 Overflow bit
1 = Receive Buffer 1 overflowed
0 = Receive Buffer 1 has not overflowed
Mode 1, 2:
RXBnOVFL: Receive Buffer n Overflow bit
1 = Receive Buffer n has overflowed
0 = Receive Buffer n has not overflowed
bit 5 TXBO: Transmitter Bus-Off bit
1 = Transmit error counter > 255
0 = Transmit error counter ≤ 255
bit 4 TXBP: Transmitter Bus Passive bit
1 = Transmit error counter > 127
0 = Transmit error counter ≤ 127
bit 3 RXBP: Receiver Bus Passive bit
1 = Receive error counter > 127
0 = Receive error counter ≤ 127
bit 2 TXWARN: Transmitter Warning bit
1 = Transmit error counter > 95
0 = Transmit error counter ≤ 95
bit 1 RXWARN: Receiver Warning bit
1 = 127 ≥ Receive error counter > 95
0 = Receive error counter ≤ 95
bit 0 EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1 = The RXWARN or the TXWARN bits are set
0 = Neither the RXWARN or the TXWARN bits are set
Legend:
C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown