Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 208 Preliminary © 2007 Microchip Technology Inc.
FIGURE 17-13: I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S
1 234 567 89 1 2 345 67 89 1 23 45 7 89
P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W
= 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master terminates transfer
SSPOV is set because SSPBUF is still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP written to ‘1’ in
If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur
software
Clock is held low until CKP is set to ‘1’
Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock
Clock is not held low because ACK = 1
BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs