Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 143
PIC18F2585/2680/4585/4680
TABLE 10-9: PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Name Function I/O TRIS Buffer Description
RE0/RD
/AN5 RE0 OUT 0 DIG LATE<0> data output.
IN 1 ST PORTE<0> data input.
RD
IN 1 TTL PSP read enable input.
AN5 IN 1 ANA A/D input channel 5. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
RE1/WR
/AN6/C1OUT RE1 OUT 0 DIG LATE<1> data output.
IN 1 ST PORTE<1> data input.
WR
IN 1 TTL PSP write enable input.
AN6 IN 1 ANA A/D input channel 6. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
C1OUT OUT 0 DIG Comparator 1 output.
RE2/CS
/AN7/C2OUT RE2 OUT 0 DIG LATE<2> data output.
IN 1 ST PORTE<2> data input.
CS
IN 1 TTL PSP chip select input.
AN7 IN 1 ANA A/D input channel 7. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
C2OUT OUT 0 DIG Comparator 2 output.
MCLR
/VPP/RE3 MCLR IN x ST External Reset input. Disabled when MCLRE Configuration bit is ‘1’.
V
PP IN x ANA High-voltage detection; used by ICSP™ operation.
RE3 IN 1 ST PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.
Legend: PWR = Power Supply; OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input;
TTL = TTL Buffer Input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE
(3)
— — — —RE3
(1,2)
RE2 RE1 RE0 52
LATE
(2)
— — — — — LATE Data Output Register 52
TRISE
(3)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 50
CMCON
(3)
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both PIC18F2X8X and PIC18F4X8X devices. All other bits are
implemented only when PORTE is implemented (i.e., PIC18F4X8X devices).
3: These registers are unimplemented on PIC18F2X8X devices.