Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 44 (8x8) 8-Bit 40 MHz I/O number 36

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Table Of Contents

Power Management Features:
Flexible Oscillator Structure:
Peripheral Highlights:
Peripheral Highlights (Continued):
Special Microcontroller Features:
Pin Diagrams
Pin Diagrams (Cont.’d)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 New Core Features
  - 1.1.1 nanoWatt Technology
  - 1.1.2 Multiple Oscillator Options and Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Oscillator Configurations
- 2.1 Oscillator Types
- 2.2 Crystal Oscillator/Ceramic Resonators
- 2.3 External Clock Input
  - FIGURE 2-3: External Clock Input Operation (EC Configuration)
  - FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
- 2.4 RC Oscillator
  - FIGURE 2-5: RC Oscillator Mode
  - FIGURE 2-6: RCIO Oscillator Mode
- 2.5 PLL Frequency Multiplier
  - 2.5.1 HSPLL Oscillator Mode
    - FIGURE 2-7: PLL Block Diagram (HS Mode)
  - 2.5.2 PLL and INTOSC
- 2.6 Internal Oscillator Block
- 2.7 Clock Sources and Oscillator Switching
- 2.8 Effects of Power-Managed Modes on the Various Clock Sources
- 2.9 Power-up Delays
  - TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
3.0 Power-Managed Modes
- 3.1 Selecting Power-Managed Modes
- 3.2 Run Modes
- 3.3 Sleep Mode
- 3.4 Idle Modes
- 3.5 Exiting Idle and Sleep Modes
4.0 Reset
- 4.1 RCON Register
  - FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 4-1: RCON: Reset Control Register
- 4.2 Master Clear (MCLR)
- 4.3 Power-on Reset (POR)
  - FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 4.4 Brown-out Reset (BOR)
- 4.5 Device Reset Timers
- 4.6 Reset State of Registers
  - TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 4-4: Initialization Conditions for All Registers
5.0 Memory Organization
- 5.1 Program Memory Organization
- 5.2 PIC18 Instruction Cycle
- 5.3 Data Memory Organization
- 5.4 Data Addressing Modes
- 5.5 Data Memory and the Extended Instruction Set
- 5.6 PIC18 Instruction Execution and the Extended Instruction Set
  - FIGURE 5-9: Remapping the Access Bank with Indexed Literal Offset Addressing Mode
6.0 Data EEPROM Memory
- 6.1 EEADR and EEADRH Registers
- 6.2 EECON1 and EECON2 Registers
  - Register 6-1: EECON1: EEPROM Control Register 1
- 6.3 Reading the Data EEPROM Memory
- 6.4 Writing to the Data EEPROM Memory
- 6.5 Write Verify
  - EXAMPLE 6-1: Data EEPROM Read
  - EXAMPLE 6-2: Data EEPROM Write
- 6.6 Operation During Code-Protect
- 6.7 Protection Against Spurious Write
- 6.8 Using the Data EEPROM
  - EXAMPLE 6-3: Data EEPROM Refresh Routine
  - TABLE 6-1: Registers Associated with Data EEPROM Memory
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: Table Read Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads From Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing a Flash Program Memory Row
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
9.0 I/O Ports
- FIGURE 9-1: Generic I/O Port Operation
- 9.1 PORTA, TRISA and LATA Registers
- 9.2 PORTB, TRISB and LATB Registers
- 9.3 PORTC, TRISC and LATC Registers
- 9.4 PORTD, TRISD and LATD Registers
- 9.5 PORTE, TRISE and LATE Registers
  - EXAMPLE 9-5: Initializing PORTE
  - 9.5.1 PORTE in 28-Pin Devices
- 9.6 Parallel Slave Port
10.0 Interrupts
- FIGURE 10-1: PIC18 Interrupt Logic
- 10.1 INTCON Registers
- 10.2 PIR Registers
  - Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
  - Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
- 10.3 PIE Registers
  - Register 10-6: PIE1: Peripheral Interrupt Enable Register 1
  - Register 10-7: PIE2: Peripheral Interrupt Enable Register 2
- 10.4 IPR Registers
  - Register 10-8: IPR1: Peripheral Interrupt Priority Register 1
  - Register 10-9: IPR2: Peripheral Interrupt Priority Register 2
- 10.5 RCON Register
  - Register 10-10: RCON: Reset Control Register
- 10.6 INTx Pin Interrupts
- 10.7 TMR0 Interrupt
- 10.8 PORTB Interrupt-on-Change
- 10.9 Context Saving During Interrupts
  - EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- 11.1 Timer0 Operation
- 11.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
- 11.3 Prescaler
  - 11.3.1 Switching Prescaler Assignment
- 11.4 Timer0 Interrupt
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram
  - FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 12.2 Timer1 16-Bit Read/Write Mode
- 12.3 Timer1 Oscillator
- 12.4 Timer1 Interrupt
- 12.5 Resetting Timer1 Using the CCP Special Event Trigger
- 12.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Timer2 Output
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON: Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram
  - FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 14.2 Timer3 16-Bit Read/Write Mode
- 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 14.4 Timer3 Interrupt
- 14.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Capture/Compare/PWM (CCP) Modules
- Register 15-1: CCPxCON: CCPx Control Register (28-Pin Devices)
- 15.1 CCP Module Configuration
  - 15.1.1 CCP Modules and Timer Resources
    - TABLE 15-1: CCP Mode – Timer Resources
  - 15.1.2 CCP2 Pin Assignment
    - TABLE 15-2: Interactions Between CCP1 and CCP2 for Timer Resources
- 15.2 Capture Mode
- 15.3 Compare Mode
- 15.4 PWM Mode
16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 16-1: CCP1CON: ECCP Control Register (40/44-Pin Devices)
- 16.1 ECCP Outputs and Configuration
  - 16.1.1 ECCP Modules and Timer Resources
- 16.2 Capture and Compare Modes
  - 16.2.1 Special Event Trigger
- 16.3 Standard PWM Mode
  - TABLE 16-1: Pin Assignments for Various ECCP1 Modes
- 16.4 Enhanced PWM Mode
17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- 17.4 I2C Mode
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)
- Register 18-1: TXSTA: Transmit Status And Control Register
- Register 18-2: RCSTA: Receive Status And Control Register
- Register 18-3: BAUDCON: Baud Rate Control Register
- 18.1 Baud Rate Generator (BRG)
- 18.2 EUSART Asynchronous Mode
- 18.3 EUSART Synchronous Master Mode
  - 18.3.1 EUSART Synchronous Master Transmission
  - 18.3.2 EUSART Synchronous Master Reception
    - FIGURE 18-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 18-8: Registers Associated with Synchronous Master Reception
- 18.4 EUSART Synchronous Slave Mode
  - 18.4.1 EUSART Synchronous Slave Transmission
    - TABLE 18-9: Registers Associated with Synchronous Slave Transmission
  - 18.4.2 EUSART Synchronous Slave Reception
    - TABLE 18-10: Registers Associated with Synchronous Slave Reception
19.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 19-1: ADCON0: A/D Control Register 0
- Register 19-2: ADCON1: A/D Control Register 1
- Register 19-3: ADCON2: A/D Control Register 2
- FIGURE 19-1: A/D Block Diagram
- FIGURE 19-2: A/D Transfer Function
- FIGURE 19-3: Analog Input Model
- 19.1 A/D Acquisition Requirements
- 19.2 Selecting and Configuring Acquisition Time
- 19.3 Selecting the A/D Conversion Clock
  - TABLE 19-1: Tad vs. Device Operating Frequencies
- 19.4 Operation in Power-Managed Modes
- 19.5 Configuring Analog Port Pins
- 19.6 A/D Conversions
- 19.7 Discharge
  - FIGURE 19-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 19-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 19.8 Use of the CCP2 Trigger
  - TABLE 19-2: Registers Associated with A/D Operation
20.0 Comparator Module
- Register 20-1: CMCON: Comparator Control Register
- 20.1 Comparator Configuration
  - FIGURE 20-1: Comparator I/O Operating Modes
- 20.2 Comparator Operation
- 20.3 Comparator Reference
- 20.4 Comparator Response Time
- 20.5 Comparator Outputs
  - FIGURE 20-3: Comparator Output Block Diagram
- 20.6 Comparator Interrupts
- 20.7 Comparator Operation During Sleep
- 20.8 Effects of a Reset
- 20.9 Analog Input Connection Considerations
  - FIGURE 20-4: Comparator Analog Input Model
  - TABLE 20-1: Registers Associated with Comparator Module
21.0 Comparator Voltage Reference Module
- 21.1 Configuring the Comparator Voltage Reference
  - Register 21-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 21-1: Comparator Voltage Reference Block Diagram
- 21.2 Voltage Reference Accuracy/Error
- 21.3 Operation During Sleep
- 21.4 Effects of a Reset
- 21.5 Connection Considerations
  - FIGURE 21-2: Voltage Reference Output Buffer Example
  - TABLE 21-1: Registers Associated with Comparator Voltage Reference
22.0 High/Low-Voltage Detect (HLVD)
- Register 22-1: HLVDCON: High/Low-Voltage Detect Control Register
- 22.1 Operation
  - FIGURE 22-1: HLVD Module Block Diagram (with External Input)
- 22.2 HLVD Setup
- 22.3 Current Consumption
- 22.4 HLVD Start-up Time
  - FIGURE 22-2: Low-Voltage Detect Operation (VDIRMAG = 0)
  - FIGURE 22-3: High-Voltage Detect Operation (VDIRMAG = 1)
- 22.5 Applications
  - FIGURE 22-4: Typical Low-Voltage Detect Application
- 22.6 Operation During Sleep
- 22.7 Effects of a Reset
  - TABLE 22-1: Registers Associated with High/Low-Voltage Detect Module
23.0 Special Features of the CPU
- 23.1 Configuration Bits
- 23.2 Watchdog Timer (WDT)
  - 23.2.1 Control Register
- 23.3 Two-Speed Start-up
  - 23.3.1 Special Considerations for Using Two-Speed Start-up
    - FIGURE 23-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
- 23.4 Fail-Safe Clock Monitor
- 23.5 Program Verification and Code Protection
- 23.6 ID Locations
- 23.7 In-Circuit Serial Programming
- 23.8 In-Circuit Debugger
  - TABLE 23-4: Debugger Resources
- 23.9 Single-Supply ICSP Programming
24.0 Instruction Set Summary
- 24.1 Standard Instruction Set
- 24.2 Extended Instruction Set
25.0 Development Support
- 25.1 MPLAB Integrated Development Environment Software
- 25.2 MPASM Assembler
- 25.3 MPLAB C18 and MPLAB C30 C Compilers
- 25.4 MPLINK Object Linker/ MPLIB Object Librarian
- 25.5 MPLAB ASM30 Assembler, Linker and Librarian
- 25.6 MPLAB SIM Software Simulator
- 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 25.8 MPLAB REAL ICE In-Circuit Emulator System
- 25.9 MPLAB ICD 2 In-Circuit Debugger
- 25.10 MPLAB PM3 Device Programmer
- 25.11 PICSTART Plus Development Programmer
- 25.12 PICkit 2 Development Programmer
- 25.13 Demonstration, Development and Evaluation Boards
26.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 26.1 DC Characteristics: Supply Voltage PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.3 DC Characteristics: PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.4 AC (Timing) Characteristics
27.0 DC and AC Characteristics Graphs and Tables
- FIGURE 27-1: Sleep Mode
- FIGURE 27-2: Typical Ipd vs. Vdd Across Temperature (Sleep Mode)
- FIGURE 27-3: Maximum Ipd vs. Vdd Across Temperature (Sleep Mode)
- FIGURE 27-4: Typical T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in Low-Power Mode)
- FIGURE 27-5: Maximum T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, TIOSC in Low-Power Mode)
- FIGURE 27-6: Typical T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in High-Power Mode)
- FIGURE 27-7: Maximum T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in High-Power Mode)
- FIGURE 27-8: Typical BOR Delta Current vs. Vdd Across Temp. (BORV = 2.7V, Sleep Mode)
- FIGURE 27-9: Typical WDT Current vs. Vdd Across Temperature (WDT Delta Current in Sleep Mode)
- FIGURE 27-10: Maximum WDT Current vs. Vdd Across Temperature (WDT Delta Current in Sleep Mode)
- FIGURE 27-11: Typical Idd Across Vdd (RC_RUN Mode, 25°C)
- FIGURE 27-12: Maximum Idd Across Vdd (RC_RUN Mode, 85°C)
- FIGURE 27-13: Typical and Maximum Idd Across Vdd (RC_RUN Mode, 31 kHz)
- FIGURE 27-14: Typical Idd Across Vdd (RC_IDLE Mode, 25°C)
- FIGURE 27-15: Maximum Idd Across Vdd (RC_IDLE Mode, -40°C-85°C)
- FIGURE 27-16: Typical and Maximum Idd Across Vdd (RC_IDLE Mode, 31 kHz)
- FIGURE 27-17: Typical and Maximum SEC_RUN Current vs. Vdd Across Temperature (T1OSC in Low-Power Mode)
- FIGURE 27-18: Typical and Maximum SEC_IDLE Current vs. Vdd Across Temperature (T1OSC in Low-Power Mode)
- FIGURE 27-19: Typical Idd vs. Fosc, 500 kHz to 4 MHz (PRI_RUN Mode (EC Clock), 25°C)
- FIGURE 27-20: Maximum Idd vs. Fosc, 500 kHz to 4 MHz (PRI_RUN Mode (EC Clock), -40°C to +125°C)
- FIGURE 27-21: Typical Idd vs. Fosc, 4 MHz to 40 MHz (PRI_RUN Mode (EC Clock), 25°C)
- FIGURE 27-22: Maximum Idd vs. Fosc, 4 MHz to 40 MHz (PRI_RUN Mode (EC Clock), -40°C to +125°C)
- FIGURE 27-23: Typical Idd vs. Fosc, HS/PLL (PRI_RUN Mode, 25°C)
- FIGURE 27-24: Maximum Idd vs. Fosc, HS/PLL (PRI_RUN Mode, -40°C)
- FIGURE 27-25: Typical Idd vs. Fosc, 500 kHz to 4 MHz (PRI_IDLE Mode, 25°C)
- FIGURE 27-26: Maximum Idd vs. Fosc, 500 kHz to 4 MHz (PRI_IDLE Mode, -40°C to +125°C)
- FIGURE 27-27: Typical Idd vs. Fosc, 4 MHz to 40 MHz (PRI_IDLE Mode, 25°C)
- FIGURE 27-28: Maximum Idd vs. Fosc, 4 MHz to 40 MHz (PRI_IDLE Mode, -40°C to +125°C)
- FIGURE 27-29: Typical Idd vs. Fosc, HS/PLL (PRI_IDLE Mode, 25°C)
- FIGURE 27-30: Maximum Idd vs. Fosc, HS/PLL (PRI_IDLE Mode, -40°C)
- FIGURE 27-31: Vin (ST) vs. Vdd, 25°C (-40°C to +125°C)
- FIGURE 27-32: Vin (TTL) vs. Vdd, 25°C (-40°C to +125°C)
- FIGURE 27-33: Vol vs. Iol (Vdd = 3.0V, -40°C to +85°C)
- FIGURE 27-34: Vol vs. Iol (Vdd = 5.0V, -40°C to +125°C)
- FIGURE 27-35: Voh vs. Ioh (Vdd = 3.0V, -40°C to +85°C)
- FIGURE 27-36: Voh vs. Ioh (Vdd = 5.0V, -40°C to +125°C)
- FIGURE 27-37: INTOSC Frequency vs. Vdd, Temperature (-40°C, +25°C, +85°C, +125°C)
- FIGURE 27-38: INTRC vs. Vdd Across Temperature (-40°C to +125°C)
- FIGURE 27-39: WDT Period vs. Vdd Across Temperature (1:1 Postscaler, -40°C to +125°C)
28.0 Packaging Information
- 28.1 Package Marking Information
- 28.1 Package Marking Information (Continued)
- 28.2 Package Details
Appendix A: Revision History
- Revision A (April 2004)
- Revision B (June 2004)
- Revision C (January 2007)
- Revision D (November 2007)
- Revision E (May 2008)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Conversion Considerations
Appendix D: Migration from Baseline to Enhanced Devices
Appendix E: Migration from Mid-Range TO Enhanced Devices
Appendix F: Migration from High-End to Enhanced Devices
INDEX
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PIC18F2525/2620/4525/4620

FIGURE 26-23: A/D CONVERSION TIMING

TABLE 26-25: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

(1)

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

987 21 0

Note 1: If the A/D clock source is selected as RC, a time of T

CY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

TCY

Param

No.

Symbol Characteristic Min Max Units Conditions

130 T

AD A/D Clock Period PIC18FXXXX 0.7 25.0

(1)

μsTOSC based, VREF ≥ 3.0V

PIC18LFXXXX 1.4 25.0

(1)

μsVDD = 2.0V;

OSC based, VREF full range

PIC18FXXXX — 1 μs A/D RC mode

PIC18LFXXXX — 3 μsV

DD = 2.0V; A/D RC mode

131 TCNV Conversion Time

(not including acquisition time) (Note 2)

11 12 TAD

132 TACQ Acquisition Time (Note 3) 1.4 — μs-40°C to +85°C

135 T

SWC Switching Time from Convert → Sample — (Note 4)

TBD T

DIS Discharge Time 0.2 — μs

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES register may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (V

DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.