Datasheet

Table Of Contents
© 2008 Microchip Technology Inc. DS39626E-page 345
PIC18F2525/2620/4525/4620
FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 26-9: BROWN-OUT RESET TIMING
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 μs
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
3.4 4.1 4.71 ms
32 TOST Oscillation Start-up Timer Period 1024 TOSC 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 55.6 65.5 75.4 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2μs
35 TBOR Brown-out Reset Pulse Width 200 μsVDD BVDD (see D005)
36 T
IVRST Time for Internal Reference
Voltage to become Stable
—2050 μs
37 T
LVD High/Low-Voltage Detect Pulse Width 200 μsVDD VLVD
38 TCSD CPU Start-up Time 10 μs
39 T
IOBST Time for INTOSC to Stabilize 1 μs
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 26-5 for load conditions.
VDD
BVDD
35
VIRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable