Datasheet

Table Of Contents
PIC18F2525/2620/4525/4620
DS39626E-page 218 © 2008 Microchip Technology Inc.
FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.