Datasheet

Table Of Contents
PIC18F2525/2620/4525/4620
DS39626E-page 160 © 2008 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN
SBOREN
(1)
RI TO PD POR BOR 48
PIR1
PSPIF
(2)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1
PSPIP
(2)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2
OSCFIE CMIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TRISB PORTB Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
TRISD PORTD Data Direction Control Register 52
TMR1L Timer1 Register Low Byte 50
TMR1H Timer1 Register High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 50
TMR2 Timer2 Register 50
T2CON
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period Register 50
TMR3L Timer3 Register Low Byte 51
TMR3H Timer3 Register High Byte 51
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1 Low Byte 51
CCPR1H Capture/Compare/PWM Register 1 High Byte 51
CCP1CON P1M1
(2)
P1M0
(2)
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1
(2)
PSSBD0
(2)
51
PWM1CON PRSEN PDC6
(2)
PDC5
(2)
PDC4
(2)
PDC3
(2)
PDC2
(2)
PDC1
(2)
PDC0
(2)
51
Legend: — = unimplemented, read as0’. Shaded cells are not used during ECCP operation.
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled
and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.