Datasheet

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Table Of Contents

Power Management Features:
Flexible Oscillator Structure:
Peripheral Highlights:
Peripheral Highlights (Continued):
Special Microcontroller Features:
Pin Diagrams
Pin Diagrams (Cont.’d)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 New Core Features
  - 1.1.1 nanoWatt Technology
  - 1.1.2 Multiple Oscillator Options and Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Oscillator Configurations
- 2.1 Oscillator Types
- 2.2 Crystal Oscillator/Ceramic Resonators
- 2.3 External Clock Input
  - FIGURE 2-3: External Clock Input Operation (EC Configuration)
  - FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
- 2.4 RC Oscillator
  - FIGURE 2-5: RC Oscillator Mode
  - FIGURE 2-6: RCIO Oscillator Mode
- 2.5 PLL Frequency Multiplier
  - 2.5.1 HSPLL Oscillator Mode
    - FIGURE 2-7: PLL Block Diagram (HS Mode)
  - 2.5.2 PLL and INTOSC
- 2.6 Internal Oscillator Block
- 2.7 Clock Sources and Oscillator Switching
- 2.8 Effects of Power-Managed Modes on the Various Clock Sources
- 2.9 Power-up Delays
  - TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
3.0 Power-Managed Modes
- 3.1 Selecting Power-Managed Modes
- 3.2 Run Modes
- 3.3 Sleep Mode
- 3.4 Idle Modes
- 3.5 Exiting Idle and Sleep Modes
4.0 Reset
- 4.1 RCON Register
  - FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 4-1: RCON: Reset Control Register
- 4.2 Master Clear (MCLR)
- 4.3 Power-on Reset (POR)
  - FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 4.4 Brown-out Reset (BOR)
- 4.5 Device Reset Timers
- 4.6 Reset State of Registers
  - TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 4-4: Initialization Conditions for All Registers
5.0 Memory Organization
- 5.1 Program Memory Organization
- 5.2 PIC18 Instruction Cycle
- 5.3 Data Memory Organization
- 5.4 Data Addressing Modes
- 5.5 Data Memory and the Extended Instruction Set
- 5.6 PIC18 Instruction Execution and the Extended Instruction Set
  - FIGURE 5-9: Remapping the Access Bank with Indexed Literal Offset Addressing Mode
6.0 Data EEPROM Memory
- 6.1 EEADR and EEADRH Registers
- 6.2 EECON1 and EECON2 Registers
  - Register 6-1: EECON1: EEPROM Control Register 1
- 6.3 Reading the Data EEPROM Memory
- 6.4 Writing to the Data EEPROM Memory
- 6.5 Write Verify
  - EXAMPLE 6-1: Data EEPROM Read
  - EXAMPLE 6-2: Data EEPROM Write
- 6.6 Operation During Code-Protect
- 6.7 Protection Against Spurious Write
- 6.8 Using the Data EEPROM
  - EXAMPLE 6-3: Data EEPROM Refresh Routine
  - TABLE 6-1: Registers Associated with Data EEPROM Memory
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: Table Read Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads From Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing a Flash Program Memory Row
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
9.0 I/O Ports
- FIGURE 9-1: Generic I/O Port Operation
- 9.1 PORTA, TRISA and LATA Registers
- 9.2 PORTB, TRISB and LATB Registers
- 9.3 PORTC, TRISC and LATC Registers
- 9.4 PORTD, TRISD and LATD Registers
- 9.5 PORTE, TRISE and LATE Registers
  - EXAMPLE 9-5: Initializing PORTE
  - 9.5.1 PORTE in 28-Pin Devices
- 9.6 Parallel Slave Port
10.0 Interrupts
- FIGURE 10-1: PIC18 Interrupt Logic
- 10.1 INTCON Registers
- 10.2 PIR Registers
  - Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
  - Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
- 10.3 PIE Registers
  - Register 10-6: PIE1: Peripheral Interrupt Enable Register 1
  - Register 10-7: PIE2: Peripheral Interrupt Enable Register 2
- 10.4 IPR Registers
  - Register 10-8: IPR1: Peripheral Interrupt Priority Register 1
  - Register 10-9: IPR2: Peripheral Interrupt Priority Register 2
- 10.5 RCON Register
  - Register 10-10: RCON: Reset Control Register
- 10.6 INTx Pin Interrupts
- 10.7 TMR0 Interrupt
- 10.8 PORTB Interrupt-on-Change
- 10.9 Context Saving During Interrupts
  - EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- 11.1 Timer0 Operation
- 11.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
- 11.3 Prescaler
  - 11.3.1 Switching Prescaler Assignment
- 11.4 Timer0 Interrupt
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram
  - FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 12.2 Timer1 16-Bit Read/Write Mode
- 12.3 Timer1 Oscillator
- 12.4 Timer1 Interrupt
- 12.5 Resetting Timer1 Using the CCP Special Event Trigger
- 12.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Timer2 Output
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON: Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram
  - FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 14.2 Timer3 16-Bit Read/Write Mode
- 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 14.4 Timer3 Interrupt
- 14.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Capture/Compare/PWM (CCP) Modules
- Register 15-1: CCPxCON: CCPx Control Register (28-Pin Devices)
- 15.1 CCP Module Configuration
  - 15.1.1 CCP Modules and Timer Resources
    - TABLE 15-1: CCP Mode – Timer Resources
  - 15.1.2 CCP2 Pin Assignment
    - TABLE 15-2: Interactions Between CCP1 and CCP2 for Timer Resources
- 15.2 Capture Mode
- 15.3 Compare Mode
- 15.4 PWM Mode
16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 16-1: CCP1CON: ECCP Control Register (40/44-Pin Devices)
- 16.1 ECCP Outputs and Configuration
  - 16.1.1 ECCP Modules and Timer Resources
- 16.2 Capture and Compare Modes
  - 16.2.1 Special Event Trigger
- 16.3 Standard PWM Mode
  - TABLE 16-1: Pin Assignments for Various ECCP1 Modes
- 16.4 Enhanced PWM Mode
17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- 17.4 I2C Mode
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)
- Register 18-1: TXSTA: Transmit Status And Control Register
- Register 18-2: RCSTA: Receive Status And Control Register
- Register 18-3: BAUDCON: Baud Rate Control Register
- 18.1 Baud Rate Generator (BRG)
- 18.2 EUSART Asynchronous Mode
- 18.3 EUSART Synchronous Master Mode
  - 18.3.1 EUSART Synchronous Master Transmission
  - 18.3.2 EUSART Synchronous Master Reception
    - FIGURE 18-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 18-8: Registers Associated with Synchronous Master Reception
- 18.4 EUSART Synchronous Slave Mode
  - 18.4.1 EUSART Synchronous Slave Transmission
    - TABLE 18-9: Registers Associated with Synchronous Slave Transmission
  - 18.4.2 EUSART Synchronous Slave Reception
    - TABLE 18-10: Registers Associated with Synchronous Slave Reception
19.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 19-1: ADCON0: A/D Control Register 0
- Register 19-2: ADCON1: A/D Control Register 1
- Register 19-3: ADCON2: A/D Control Register 2
- FIGURE 19-1: A/D Block Diagram
- FIGURE 19-2: A/D Transfer Function
- FIGURE 19-3: Analog Input Model
- 19.1 A/D Acquisition Requirements
- 19.2 Selecting and Configuring Acquisition Time
- 19.3 Selecting the A/D Conversion Clock
  - TABLE 19-1: Tad vs. Device Operating Frequencies
- 19.4 Operation in Power-Managed Modes
- 19.5 Configuring Analog Port Pins
- 19.6 A/D Conversions
- 19.7 Discharge
  - FIGURE 19-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 19-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 19.8 Use of the CCP2 Trigger
  - TABLE 19-2: Registers Associated with A/D Operation
20.0 Comparator Module
- Register 20-1: CMCON: Comparator Control Register
- 20.1 Comparator Configuration
  - FIGURE 20-1: Comparator I/O Operating Modes
- 20.2 Comparator Operation
- 20.3 Comparator Reference
- 20.4 Comparator Response Time
- 20.5 Comparator Outputs
  - FIGURE 20-3: Comparator Output Block Diagram
- 20.6 Comparator Interrupts
- 20.7 Comparator Operation During Sleep
- 20.8 Effects of a Reset
- 20.9 Analog Input Connection Considerations
  - FIGURE 20-4: Comparator Analog Input Model
  - TABLE 20-1: Registers Associated with Comparator Module
21.0 Comparator Voltage Reference Module
- 21.1 Configuring the Comparator Voltage Reference
  - Register 21-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 21-1: Comparator Voltage Reference Block Diagram
- 21.2 Voltage Reference Accuracy/Error
- 21.3 Operation During Sleep
- 21.4 Effects of a Reset
- 21.5 Connection Considerations
  - FIGURE 21-2: Voltage Reference Output Buffer Example
  - TABLE 21-1: Registers Associated with Comparator Voltage Reference
22.0 High/Low-Voltage Detect (HLVD)
- Register 22-1: HLVDCON: High/Low-Voltage Detect Control Register
- 22.1 Operation
  - FIGURE 22-1: HLVD Module Block Diagram (with External Input)
- 22.2 HLVD Setup
- 22.3 Current Consumption
- 22.4 HLVD Start-up Time
  - FIGURE 22-2: Low-Voltage Detect Operation (VDIRMAG = 0)
  - FIGURE 22-3: High-Voltage Detect Operation (VDIRMAG = 1)
- 22.5 Applications
  - FIGURE 22-4: Typical Low-Voltage Detect Application
- 22.6 Operation During Sleep
- 22.7 Effects of a Reset
  - TABLE 22-1: Registers Associated with High/Low-Voltage Detect Module
23.0 Special Features of the CPU
- 23.1 Configuration Bits
- 23.2 Watchdog Timer (WDT)
  - 23.2.1 Control Register
- 23.3 Two-Speed Start-up
  - 23.3.1 Special Considerations for Using Two-Speed Start-up
    - FIGURE 23-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
- 23.4 Fail-Safe Clock Monitor
- 23.5 Program Verification and Code Protection
- 23.6 ID Locations
- 23.7 In-Circuit Serial Programming
- 23.8 In-Circuit Debugger
  - TABLE 23-4: Debugger Resources
- 23.9 Single-Supply ICSP Programming
24.0 Instruction Set Summary
- 24.1 Standard Instruction Set
- 24.2 Extended Instruction Set
25.0 Development Support
- 25.1 MPLAB Integrated Development Environment Software
- 25.2 MPASM Assembler
- 25.3 MPLAB C18 and MPLAB C30 C Compilers
- 25.4 MPLINK Object Linker/ MPLIB Object Librarian
- 25.5 MPLAB ASM30 Assembler, Linker and Librarian
- 25.6 MPLAB SIM Software Simulator
- 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 25.8 MPLAB REAL ICE In-Circuit Emulator System
- 25.9 MPLAB ICD 2 In-Circuit Debugger
- 25.10 MPLAB PM3 Device Programmer
- 25.11 PICSTART Plus Development Programmer
- 25.12 PICkit 2 Development Programmer
- 25.13 Demonstration, Development and Evaluation Boards
26.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 26.1 DC Characteristics: Supply Voltage PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.2 DC Characteristics: Power-Down and Supply Current PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.3 DC Characteristics: PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial)
- 26.4 AC (Timing) Characteristics
27.0 DC and AC Characteristics Graphs and Tables
- FIGURE 27-1: Sleep Mode
- FIGURE 27-2: Typical Ipd vs. Vdd Across Temperature (Sleep Mode)
- FIGURE 27-3: Maximum Ipd vs. Vdd Across Temperature (Sleep Mode)
- FIGURE 27-4: Typical T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in Low-Power Mode)
- FIGURE 27-5: Maximum T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, TIOSC in Low-Power Mode)
- FIGURE 27-6: Typical T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in High-Power Mode)
- FIGURE 27-7: Maximum T1OSC Delta Current vs. Vdd Across Temp. (Device in Sleep, T1OSC in High-Power Mode)
- FIGURE 27-8: Typical BOR Delta Current vs. Vdd Across Temp. (BORV = 2.7V, Sleep Mode)
- FIGURE 27-9: Typical WDT Current vs. Vdd Across Temperature (WDT Delta Current in Sleep Mode)
- FIGURE 27-10: Maximum WDT Current vs. Vdd Across Temperature (WDT Delta Current in Sleep Mode)
- FIGURE 27-11: Typical Idd Across Vdd (RC_RUN Mode, 25°C)
- FIGURE 27-12: Maximum Idd Across Vdd (RC_RUN Mode, 85°C)
- FIGURE 27-13: Typical and Maximum Idd Across Vdd (RC_RUN Mode, 31 kHz)
- FIGURE 27-14: Typical Idd Across Vdd (RC_IDLE Mode, 25°C)
- FIGURE 27-15: Maximum Idd Across Vdd (RC_IDLE Mode, -40°C-85°C)
- FIGURE 27-16: Typical and Maximum Idd Across Vdd (RC_IDLE Mode, 31 kHz)
- FIGURE 27-17: Typical and Maximum SEC_RUN Current vs. Vdd Across Temperature (T1OSC in Low-Power Mode)
- FIGURE 27-18: Typical and Maximum SEC_IDLE Current vs. Vdd Across Temperature (T1OSC in Low-Power Mode)
- FIGURE 27-19: Typical Idd vs. Fosc, 500 kHz to 4 MHz (PRI_RUN Mode (EC Clock), 25°C)
- FIGURE 27-20: Maximum Idd vs. Fosc, 500 kHz to 4 MHz (PRI_RUN Mode (EC Clock), -40°C to +125°C)
- FIGURE 27-21: Typical Idd vs. Fosc, 4 MHz to 40 MHz (PRI_RUN Mode (EC Clock), 25°C)
- FIGURE 27-22: Maximum Idd vs. Fosc, 4 MHz to 40 MHz (PRI_RUN Mode (EC Clock), -40°C to +125°C)
- FIGURE 27-23: Typical Idd vs. Fosc, HS/PLL (PRI_RUN Mode, 25°C)
- FIGURE 27-24: Maximum Idd vs. Fosc, HS/PLL (PRI_RUN Mode, -40°C)
- FIGURE 27-25: Typical Idd vs. Fosc, 500 kHz to 4 MHz (PRI_IDLE Mode, 25°C)
- FIGURE 27-26: Maximum Idd vs. Fosc, 500 kHz to 4 MHz (PRI_IDLE Mode, -40°C to +125°C)
- FIGURE 27-27: Typical Idd vs. Fosc, 4 MHz to 40 MHz (PRI_IDLE Mode, 25°C)
- FIGURE 27-28: Maximum Idd vs. Fosc, 4 MHz to 40 MHz (PRI_IDLE Mode, -40°C to +125°C)
- FIGURE 27-29: Typical Idd vs. Fosc, HS/PLL (PRI_IDLE Mode, 25°C)
- FIGURE 27-30: Maximum Idd vs. Fosc, HS/PLL (PRI_IDLE Mode, -40°C)
- FIGURE 27-31: Vin (ST) vs. Vdd, 25°C (-40°C to +125°C)
- FIGURE 27-32: Vin (TTL) vs. Vdd, 25°C (-40°C to +125°C)
- FIGURE 27-33: Vol vs. Iol (Vdd = 3.0V, -40°C to +85°C)
- FIGURE 27-34: Vol vs. Iol (Vdd = 5.0V, -40°C to +125°C)
- FIGURE 27-35: Voh vs. Ioh (Vdd = 3.0V, -40°C to +85°C)
- FIGURE 27-36: Voh vs. Ioh (Vdd = 5.0V, -40°C to +125°C)
- FIGURE 27-37: INTOSC Frequency vs. Vdd, Temperature (-40°C, +25°C, +85°C, +125°C)
- FIGURE 27-38: INTRC vs. Vdd Across Temperature (-40°C to +125°C)
- FIGURE 27-39: WDT Period vs. Vdd Across Temperature (1:1 Postscaler, -40°C to +125°C)
28.0 Packaging Information
- 28.1 Package Marking Information
- 28.1 Package Marking Information (Continued)
- 28.2 Package Details
Appendix A: Revision History
- Revision A (April 2004)
- Revision B (June 2004)
- Revision C (January 2007)
- Revision D (November 2007)
- Revision E (May 2008)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Conversion Considerations
Appendix D: Migration from Baseline to Enhanced Devices
Appendix E: Migration from Mid-Range TO Enhanced Devices
Appendix F: Migration from High-End to Enhanced Devices
INDEX
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PIC18F2525/2620/4525/4620

Data Sheet

28/40/44-Pin

Enhanced Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

Summary of content (412 pages)

PAGE 1
PIC18F2525/2620/4525/4620 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2008 Microchip Technology Inc.
PAGE 2
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 3
PIC18F2525/2620/4525/4620 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Power Management Features: Peripheral Highlights (Continued): • • • • • • • • • • • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-wake-up on Start bit - Auto-Baud De
PAGE 4
PIC18F2525/2620/4525/4620 Pin Diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18F2525 PIC18F2620 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC18F4525 28-Pin SPDIP, SOIC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/I
PAGE 5
PIC18F2525/2620/4525/4620 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2(1) NC Pin Diagrams (Cont.
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PIC18F2525/2620/4525/4620 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power-Managed Modes .............................................................
PAGE 7
PIC18F2525/2620/4525/4620 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PAGE 9
PIC18F2525/2620/4525/4620 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2525 • PIC18LF2525 • PIC18F2620 • PIC18LF2620 • PIC18F4525 • PIC18LF4525 • PIC18F4620 • PIC18LF4620 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory.
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PIC18F2525/2620/4525/4620 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control.
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PIC18F2525/2620/4525/4620 TABLE 1-1: DEVICE FEATURES Features PIC18F2525 PIC18F2620 PIC18F4525 PIC18F4620 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 49152 65536 49152 65536 Program Memory (Instructions) 24576 32768 24576 32768 Data Memory (Bytes) 3968 3968 3968 3968 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 19 19 20 20 Ports A, B, C, (E) Ports A, B, C, (E) 4 4 Interrupt Sources I/O Ports Timers Ports A, B, C, D, E
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PIC18F2525/2620/4525/4620 FIGURE 1-1: PIC18F2525/2620 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 Data Memory (3.
PAGE 13
PIC18F2525/2620/4525/4620 FIGURE 1-2: PIC18F4525/4620 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> inc/dec logic Data Memory (3.
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PIC18F2525/2620/4525/4620 TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, SOIC MCLR/VPP/RE3 MCLR Buffer Type I ST P I ST 1 VPP RE3 OSC1/CLKI/RA7 OSC1 Pin Type 9 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F2525/2620/4525/4620 TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1.
PAGE 16
PIC18F2525/2620/4525/4620 TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PAGE 17
PIC18F2525/2620/4525/4620 TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, SOIC Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 I/O O I ST — ST I/O I I/O ST Analog ST Digital I/O. Timer1 oscillator input.
PAGE 18
PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP MCLR/VPP/RE3 MCLR 1 Pin Buffer Type Type QFN TQFP 18 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 32 ST P I ST 30 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 I I/O 14 33 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer Type Type QFN TQFP Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 19 20 21 22 23 24 19 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O.
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PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer Type Type QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer Type Type QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 16 RC2/CCP1/P1A RC2 CCP1 P1A 17 RC3/SCK/SCL RC3 SCK 18 34 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 42 43 44 1 ST — ST Digital I/O. Timer1 oscillator output.
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PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer Type Type QFN TQFP Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.
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PIC18F2525/2620/4525/4620 TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer Type Type QFN TQFP Description PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD 8 25 25 AN5 RE1/WR/AN6 RE1 WR 9 26 10 27 — I Analog I/O I ST TTL I Analog I/O I ST TTL I Analog Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog input 6.
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PIC18F2525/2620/4525/4620 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2525/2620/4525/4620 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL Enabled 5. RC External Resistor/Capacitor with FOSC/4 Output on RA6 6.
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PIC18F2525/2620/4525/4620 TABLE 2-2: Osc Type CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 30 pF 30 pF XT 1 MHz 4 MHz 15 pF 15 pF 15 pF 15 pF 4 MHz 10 MHz 20 MHz 25 MHz 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF HS An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 Clock from Ext.
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PIC18F2525/2620/4525/4620 2.4 RC Oscillator 2.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings.
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PIC18F2525/2620/4525/4620 2.6 Internal Oscillator Block The PIC18F2525/2620/4525/4620 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock.
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PIC18F2525/2620/4525/4620 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
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PIC18F2525/2620/4525/4620 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2525/2620/ 4525/4620 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F2525/2620/4525/4620 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
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PIC18F2525/2620/4525/4620 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
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PIC18F2525/2620/4525/4620 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Inte
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PIC18F2525/2620/4525/4620 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
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PIC18F2525/2620/4525/4620 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F2525/2620/4525/4620 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
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PIC18F2525/2620/4525/4620 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
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PIC18F2525/2620/4525/4620 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC PC + 2 PC + 4 Clock transition typically occurs within 2-4 TOSC.
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PIC18F2525/2620/4525/4620 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4).
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PIC18F2525/2620/4525/4620 3.3 Sleep Mode 3.4 The power-managed Sleep mode in the PIC18F2525/ 2620/4525/4620 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch.
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PIC18F2525/2620/4525/4620 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
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PIC18F2525/2620/4525/4620 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
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PIC18F2525/2620/4525/4620 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT, HS or HSPLL modes.
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PIC18F2525/2620/4525/4620 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1.
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PIC18F2525/2620/4525/4620 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN:
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PIC18F2525/2620/4525/4620 4.2 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 4-2: In PIC18F2525/2620/4525/4620 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 9.
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PIC18F2525/2620/4525/4620 4.4 Brown-out Reset (BOR) PIC18F2525/2620/4525/4620 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits.
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PIC18F2525/2620/4525/4620 4.5 4.5.3 Device Reset Timers PIC18F2525/2620/4525/4620 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.
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PIC18F2525/2620/4525/4620 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39626E-page 46
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PIC18F2525/2620/4525/4620 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
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PIC18F2525/2620/4525/4620 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2525 2620 4525 4620 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2525 2620 4525 4620 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2525 2620 4525 4620 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2525 2620 4525 4620 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2525 2620 4525 4620 ---0 00
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PIC18F2525/2620/4525/4620 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt FSR1H 2525 2620 4525 4620 ---- 0000 ---- 0000 ---- uuuu FSR1L 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2525 2620 4525 4620 ---- 0000 ---- 0000 ---- uuuu INDF2 2525 2620 4525 4620 N/A N/A N/A Register POSTINC2 2525 2620 4525 4620 N/A N/A N/A
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PIC18F2525/2620/4525/4620 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt ADRESH 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2525 2620 4525 4620 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2525 2620 4525 4620 --00 0000 --00 0000 --uu uuuu ADCON1 2525 2620 4525 4620 --00 0qqq --00 0qqq --uu uuuu Register ADCON2 2525 2620 45
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PIC18F2525/2620/4525/4620 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt IPR2 2525 2620 4525 4620 11-1 1111 11-1 1111 uu-u uuuu PIR2 2525 2620 4525 4620 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2525 2620 4525 4620 00-0 0000 00-0 0000 uu-u uuuu IPR1 2525 2620 4525 4620 1111 1111 1111 1111 uuuu uuuu 2525 2620 4525 4620 -11
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PIC18F2525/2620/4525/4620 MEMORY ORGANIZATION 5.1 There are three types of memory in PIC18 enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
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PIC18F2525/2620/4525/4620 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
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PIC18F2525/2620/4525/4620 5.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
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PIC18F2525/2620/4525/4620 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset.
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PIC18F2525/2620/4525/4620 5.2 5.2.2 PIC18 Instruction Cycle 5.2.1 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC18F2525/2620/4525/4620 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”).
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PIC18F2525/2620/4525/4620 5.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory.
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PIC18F2525/2620/4525/4620 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2525/2620/4525/4620 DEVICES BSR<3:0> = 0000 00h Access RAM FFh 00h GPR Bank 0 = 0001 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 DS39626E-page 60 1FFh 200h FFh 00h Bank 2 Bank 3 Bank 4 Bank 5 2FFh 300h GPR 3FFh 400h FFh 00h Bank 12 When a = 1: The BSR specifies the Bank used by the instruction.
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PIC18F2525/2620/4525/4620 FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 0 Data Memory BSR(1) 7 0 0 0 0 0 0 1 1 000h 00h Bank 0 100h Bank 1 Bank Select(2) FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h 200h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh 00h E00h Bank 14 F00h Bank 15 FFFh Note 1: 2: 5.3.
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PIC18F2525/2620/4525/4620 5.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The reset and interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral.
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PIC18F2525/2620/4525/4620 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 49, 54 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 54 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 54 00-0 0000 49, 55 ---0 0000 49, 54 TOSU STKPTR STKFUL(6) STKUNF(6) — PCLATU — — — Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR SP4 SP3 SP2 SP1 SP0 Holding Register
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PIC18F2525/2620/4525/4620 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TMR0H Timer0 Register High Byte 0000 0000 50, 125 TMR0L Timer0 Register Low Byte xxxx xxxx 50, 125 50, 123 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3
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PIC18F2525/2620/4525/4620 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 206 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51, 206 RCREG EUSART Receive Register 0000 0000 51, 213 TXREG EUSART Transmit Register 0000 0000 51, 211 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH RCSTA SPEN
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PIC18F2525/2620/4525/4620 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
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PIC18F2525/2620/4525/4620 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
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PIC18F2525/2620/4525/4620 5.4.3.1 FSR Registers and the INDF Operand 5.4.3.2 At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
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PIC18F2525/2620/4525/4620 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.
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PIC18F2525/2620/4525/4620 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory.
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PIC18F2525/2620/4525/4620 5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET ADDRESSING MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
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PIC18F2525/2620/4525/4620 6.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
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PIC18F2525/2620/4525/4620 REGISTER 6-1: R/W-x EECON1: EEPROM CONTROL REGISTER 1 R/W-x EEPGD CFGS U-0 — R/W-0 FREE R/W-x WRERR (1) R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Set only bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM
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PIC18F2525/2620/4525/4620 6.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
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PIC18F2525/2620/4525/4620 6.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “Special Features of the CPU” for additional information. 6.
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PIC18F2525/2620/4525/4620 TABLE 6-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 GIE/GIEH PEIE/GIEL — Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — — — — — Bit 1 Bit 0 INT0IF RBIF EEPROM Address Register High Byte Reset Values on page 49 51 EEADR EEPROM Address Register 51 EEDATA EEPROM Data Register 51 EECON2 EEPROM Control Register 2 (not a physical register) 51 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP
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PIC18F2525/2620/4525/4620 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
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PIC18F2525/2620/4525/4620 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
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PIC18F2525/2620/4525/4620 REGISTER 7-1: R/W-x EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x EEPGD U-0 — CFGS R/W-0 FREE R/W-x WRERR (1) R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Set only bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data E
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PIC18F2525/2620/4525/4620 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
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PIC18F2525/2620/4525/4620 7.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words.
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PIC18F2525/2620/4525/4620 7.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 7.4.
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PIC18F2525/2620/4525/4620 7.5 Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory.
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PIC18F2525/2620/4525/4620 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ;
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PIC18F2525/2620/4525/4620 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 7.5.
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PIC18F2525/2620/4525/4620 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
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PIC18F2525/2620/4525/4620 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
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PIC18F2525/2620/4525/4620 9.0 I/O PORTS Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
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PIC18F2525/2620/4525/4620 TABLE 9-1: PORTA I/O SUMMARY Pin RA0/AN0 RA1/AN1 RA2/AN2/ VREF-/CVREF RA3/AN3/VREF+ Function TRIS Setting I/O I/O Type RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled.
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PIC18F2525/2620/4525/4620 TABLE 9-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 (1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register Reset Values on page 52 52 52 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51 CVRCON CVREN CV
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PIC18F2525/2620/4525/4620 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
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PIC18F2525/2620/4525/4620 TABLE 9-3: Pin RB0/INT0/FLT0/ AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2 PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB0 0 O DIG LATB<0> data output; not affected by analog input. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External interrupt 0 input. INT0 1 I ST FLT0 1 I ST AN12 1 I ANA A/D input channel 12.(1) RB1 0 O DIG LATB<1> data output; not affected by analog input.
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PIC18F2525/2620/4525/4620 TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52 LATB PORTB Data Latch Register (Read and Write to Data Latch) 52 TRISB PORTB Data Direction Control Register 52 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTEDG0 INTEDG1 INTEDG2 RBIE TMR0IF INT0IF RBIF 49 — TMR0IP — RBIP 49 INTCON2 RBPU INTCON3 INT2IP INT1IP — INT2IE IN
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PIC18F2525/2620/4525/4620 9.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
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PIC18F2525/2620/4525/4620 TABLE 9-5: Pin RC0/T1OSO/ T13CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A PORTC I/O SUMMARY Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input.
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PIC18F2525/2620/4525/4620 TABLE 9-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52 LATC PORTC Data Latch Register (Read and Write to Data Latch) 52 TRISC PORTC Data Direction Control Register 52 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 9.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on 40/44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
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PIC18F2525/2620/4525/4620 TABLE 9-7: Pin RD0/PSP0 PORTD I/O SUMMARY Function TRIS Setting I/O I/O Type RD0 0 O DIG 1 I ST PORTD<0> data input. x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. LATD<2> data output.
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PIC18F2525/2620/4525/4620 TABLE 9-8: Name PORTD SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Register (Read and Write to Data Latch) 52 TRISD PORTD Data Direction Control Register 52 TRISE CCP1CON IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51 Legend: — = unimplemented, read as ‘0’.
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PIC18F2525/2620/4525/4620 9.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2525/2620/4525/ 4620 device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE.
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PIC18F2525/2620/4525/4620 REGISTER 9-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output B
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PIC18F2525/2620/4525/4620 TABLE 9-9: PORTE I/O SUMMARY Pin Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 MCLR/VPP/RE3(1) Legend: Note 1: 2: PORTE (2) RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D input channel 5; default input configuration on POR.
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PIC18F2525/2620/4525/4620 9.6 Note: Parallel Slave Port The Parallel Slave Port is only available on 40/44-pin devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 9-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation as long as the Enhanced CCP module is not operating in dual output or quad output PWM mode.
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PIC18F2525/2620/4525/4620 FIGURE 9-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 9-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52 LATD PORTD Data Latch Regis
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PIC18F2525/2620/4525/4620 10.0 INTERRUPTS The PIC18F2525/2620/4525/4620 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the lowpriority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
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PIC18F2525/2620/4525/4620 FIGURE 10-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP SSPIF SSPIE SSPIP GIE/GIEH ADIF ADIE ADIP IPEN IPEN RCIF RCIE RCIP PEIE/GIEL IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation SSPIF SSPIE SSPIP Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP ADIF A
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PIC18F2525/2620/4525/4620 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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PIC18F2525/2620/4525/4620 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt
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PIC18F2525/2620/4525/4620 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 INT2IP INT1IP U-0 R/W-0 R/W-0 — INT2IE INT1IE U-0 R/W-0 R/W-0 — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priori
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PIC18F2525/2620/4525/4620 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). REGISTER 10-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
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PIC18F2525/2620/4525/4620 REGISTER 10-5: R/W-0 PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF OSCFIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in sof
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PIC18F2525/2620/4525/4620 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
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PIC18F2525/2620/4525/4620 REGISTER 10-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimple
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PIC18F2525/2620/4525/4620 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
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PIC18F2525/2620/4525/4620 REGISTER 10-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Lo
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PIC18F2525/2620/4525/4620 10.5 RCON Register The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities.
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PIC18F2525/2620/4525/4620 10.6 INTx Pin Interrupts 10.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
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PIC18F2525/2620/4525/4620 11.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 11-1: The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection.
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PIC18F2525/2620/4525/4620 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
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PIC18F2525/2620/4525/4620 11.3 11.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
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PIC18F2525/2620/4525/4620 12.
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PIC18F2525/2620/4525/4620 12.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
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PIC18F2525/2620/4525/4620 12.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer.
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PIC18F2525/2620/4525/4620 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
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PIC18F2525/2620/4525/4620 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
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PIC18F2525/2620/4525/4620 13.0 TIMER2 MODULE 13.
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PIC18F2525/2620/4525/4620 13.2 Timer2 Interrupt 13.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
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PIC18F2525/2620/4525/4620 14.0 TIMER3 MODULE The Timer3 module timer/counter incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 14-1: A simplified block diagram of the Timer3 module is shown in Figure 14-1.
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PIC18F2525/2620/4525/4620 14.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
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PIC18F2525/2620/4525/4620 14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 14-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
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PIC18F2525/2620/4525/4620 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2525/2620/4525/4620 devices all have two CCP (Capture/Compare/PWM) modules. Each module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. In 28-pin devices, the two standard CCP modules (CCP1 and CCP2) operate as described in this chapter.
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PIC18F2525/2620/4525/4620 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1, 2 or 3, depending on the mode selected.
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PIC18F2525/2620/4525/4620 15.2 15.2.3 Capture Mode When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin.
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PIC18F2525/2620/4525/4620 15.3 15.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 15.3.
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PIC18F2525/2620/4525/4620 TABLE 15-3: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 (1) — RI TO PD POR BOR 48 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 (2) PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCON IPE
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PIC18F2525/2620/4525/4620 15.4 15.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: Clearing the CCP2CON register will force the RB3 or RC1 output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch.
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PIC18F2525/2620/4525/4620 The CCPR2H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. EQUATION 15-3: F OSC log ⎛ ---------------⎞ ⎝ F PWM⎠ PWM Resolution (max) = -----------------------------bits log ( 2 ) When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP2 pin is cleared.
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PIC18F2525/2620/4525/4620 TABLE 15-5: Name INTCON REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL (1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 — RI TO PD POR BOR 48 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE (2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 RCON IPEN SBOREN Bit 5 TRISB PORTB
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PIC18F2525/2620/4525/4620 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE Note: The ECCP module is implemented only in 40/44-pin devices. In PIC18F4525/4620 devices, CCP1 is implemented as a standard CCP module with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 16-1: Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”.
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PIC18F2525/2620/4525/4620 In addition to the expanded range of modes available through the CCP1CON and ECCP1AS registers, the ECCP module has an additional register associated with Enhanced PWM operation and auto-shutdown features; it is: • PWM1CON (PWM Configuration) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTC and PORTD.
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PIC18F2525/2620/4525/4620 16.4 16.4.1 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low).
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PIC18F2525/2620/4525/4620 16.4.2 PWM DUTY CYCLE EQUATION 16-3: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. log FOSC FPWM PWM Resolution (max) = log(2) ( Note: EQUATION 16-2: 16.4.
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PIC18F2525/2620/4525/4620 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 CCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON <7:6> 00 (Single Output) SIGNAL 0 Duty C
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PIC18F2525/2620/4525/4620 16.4.4 HALF-BRIDGE MODE FIGURE 16-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals.
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PIC18F2525/2620/4525/4620 16.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 16-6. FIGURE 16-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches.
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PIC18F2525/2620/4525/4620 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F4X2X FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 16.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows user to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
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PIC18F2525/2620/4525/4620 FIGURE 16-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
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PIC18F2525/2620/4525/4620 16.4.6 Note: PROGRAMMABLE DEAD-BAND DELAY A shutdown event can be caused by either of the comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a low digital signal on FLT0 can also trigger a shutdown.
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PIC18F2525/2620/4525/4620 REGISTER 16-3: ECCP1AS: ECCP AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs ar
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PIC18F2525/2620/4525/4620 16.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared.
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PIC18F2525/2620/4525/4620 16.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. 3. If auto-shutdown is required, do the following: • Disable auto-shutdown (ECCP1AS = 0) • Configure source (FLT0, Comparator 1 or Comparator 2) • Wait for non-shutdown condition 4.
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PIC18F2525/2620/4525/4620 TABLE 16-3: Name INTCON RCON REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL IPEN SBOREN(1) Reset Values on page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 — RI TO PD POR BOR 48 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
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PIC18F2525/2620/4525/4620 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC18F2525/2620/4525/4620 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
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PIC18F2525/2620/4525/4620 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word
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PIC18F2525/2620/4525/4620 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
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PIC18F2525/2620/4525/4620 17.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
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PIC18F2525/2620/4525/4620 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI operation is only going to receive, the SDO output could be disabled (programmed as an input).
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PIC18F2525/2620/4525/4620 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>).
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PIC18F2525/2620/4525/4620 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit
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PIC18F2525/2620/4525/4620 17.3.8 OPERATION IN POWER-MANAGED MODES 17.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 2.7 “Clock Sources and Oscillator Switching” for additional information.
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PIC18F2525/2620/4525/4620 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
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PIC18F2525/2620/4525/4620 REGISTER 17-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz) 0 = Slew rate control enabled for Hig
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PIC18F2525/2620/4525/4620 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions
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PIC18F2525/2620/4525/4620 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(2) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received i
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PIC18F2525/2620/4525/4620 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation.
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PIC18F2525/2620/4525/4620 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set, or bit, SSPOV (SSPCON1<6>), is set.
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DS39626E-page 176 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS39626E-page 178 2 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared in
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PIC18F2525/2620/4525/4620 17.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
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PIC18F2525/2620/4525/4620 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
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DS39626E-page 182 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
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© 2008 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
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PIC18F2525/2620/4525/4620 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
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PIC18F2525/2620/4525/4620 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
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PIC18F2525/2620/4525/4620 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
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PIC18F2525/2620/4525/4620 17.4.7 BAUD RATE Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting.
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PIC18F2525/2620/4525/4620 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
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PIC18F2525/2620/4525/4620 17.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
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PIC18F2525/2620/4525/4620 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
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PIC18F2525/2620/4525/4620 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
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DS39626E-page 192 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = ‘0’ R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting
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PIC18F2525/2620/4525/4620 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
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PIC18F2525/2620/4525/4620 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.
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PIC18F2525/2620/4525/4620 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
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PIC18F2525/2620/4525/4620 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
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PIC18F2525/2620/4525/4620 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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PIC18F2525/2620/4525/4620 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31).
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PIC18F2525/2620/4525/4620 18.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
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PIC18F2525/2620/4525/4620 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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PIC18F2525/2620/4525/4620 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset)
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PIC18F2525/2620/4525/4620 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 =
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PIC18F2525/2620/4525/4620 18.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also control the baud rate. In Synchronous mode, BRGH is ignored.
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PIC18F2525/2620/4525/4620 EXAMPLE 18-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
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PIC18F2525/2620/4525/4620 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.
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PIC18F2525/2620/4525/4620 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.02 8332 2082 0.300 1.200 0.06 1040 2.399 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 2.402 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.02 -0.03 4165 1041 0.300 1.200 -0.03 520 2.404 SPBRG value FOSC = 8.
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PIC18F2525/2620/4525/4620 18.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
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PIC18F2525/2620/4525/4620 FIGURE 18-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
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PIC18F2525/2620/4525/4620 18.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software.
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PIC18F2525/2620/4525/4620 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 1 TCY TXIF bit (Interrupt Reg.
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PIC18F2525/2620/4525/4620 18.2.2 EUSART ASYNCHRONOUS RECEIVER 18.2.3 The receiver block diagram is shown in Figure 18-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
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PIC18F2525/2620/4525/4620 FIGURE 18-7: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit 0 bit 7/8 Stop bit bit 1 Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set.
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PIC18F2525/2620/4525/4620 18.2.4.1 Special Considerations Using Auto-Wake-up 18.2.4.2 Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-OfCharacter (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus.
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PIC18F2525/2620/4525/4620 18.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift Register is loaded with data.
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PIC18F2525/2620/4525/4620 18.3 EUSART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit, TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
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PIC18F2525/2620/4525/4620 FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 18-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE(1) AD
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PIC18F2525/2620/4525/4620 18.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8.
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PIC18F2525/2620/4525/4620 18.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.1 EUSART SYNCHRONOUS SLAVE TRANSMISSION 2. 3. 4. 5. 6.
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PIC18F2525/2620/4525/4620 18.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F2525/2620/4525/4620 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 19-2, configures the functions of the port pins.
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PIC18F2525/2620/4525/4620 REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-q(1) R/W-q(1) R/W-q(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG3: PCFG0 AN6(2) AN5(2) AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN7(2) bit 3-0 AN8 VCFG0: Voltage Reference Configuration bit (VREF+
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PIC18F2525/2620/4525/4620 REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20
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PIC18F2525/2620/4525/4620 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O.
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PIC18F2525/2620/4525/4620 Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. 6. 7. FIGURE 19-2: 3FFh 1. 3FEh FIGURE 19-3: 002h 001h 1023 LSB 1023.5 LSB 1022 LSB 1022.
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PIC18F2525/2620/4525/4620 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F2525/2620/4525/4620 19.2 Selecting and Configuring Acquisition Time 19.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
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PIC18F2525/2620/4525/4620 19.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started.
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PIC18F2525/2620/4525/4620 19.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 19-4 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F2525/2620/4525/4620 19.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero.
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PIC18F2525/2620/4525/4620 20.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section 21.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
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PIC18F2525/2620/4525/4620 20.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 20-1. Bits, CM2:CM0 of the CMCON register, are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode.
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PIC18F2525/2620/4525/4620 20.2 20.3.2 Comparator Operation A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
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PIC18F2525/2620/4525/4620 + To RA4 or RA5 pin - Port pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 20-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From other Comparator Reset 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
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PIC18F2525/2620/4525/4620 20.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 20-4.
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PIC18F2525/2620/4525/4620 21.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 21-1.
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PIC18F2525/2620/4525/4620 FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R 16-to-1 MUX R R 16 Steps CVREF R R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 21.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails.
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PIC18F2525/2620/4525/4620 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 21-1: Name CVREF Output R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
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PIC18F2525/2620/4525/4620 22.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2525/2620/4525/4620 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set.
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PIC18F2525/2620/4525/4620 22.1 Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The “trip point” voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module.
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PIC18F2525/2620/4525/4620 22.2 HLVD Setup The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>). Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt.
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PIC18F2525/2620/4525/4620 FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, the ability to detect a drop below or rise above a particular threshol
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PIC18F2525/2620/4525/4620 22.6 Operation During Sleep 22.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 22-1: Name A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
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PIC18F2525/2620/4525/4620 23.0 SPECIAL FEATURES OF THE CPU The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays.
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PIC18F2525/2620/4525/4620 REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabl
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PIC18F2525/2620/4525/4620 REGISTER 23-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — U-0 — — R/P-1 BORV1 (1) R/P-1 BORV0 (1) R/P-1 BOREN1 R/P-1 (2) R/P-1 BOREN0 bit 7 (2) PWRTEN(2) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . .
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PIC18F2525/2620/4525/4620 REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101
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PIC18F2525/2620/4525/4620 REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemen
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PIC18F2525/2620/4525/4620 REGISTER 23-6: U-0 CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 — — U-0 — U-0 — R/C-1 (1) CP3 R/C-1 R/C-1 R/C-1 CP2 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh) code-p
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PIC18F2525/2620/4525/4620 REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-007FF
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PIC18F2525/2620/4525/4620 REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from table reads execu
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PIC18F2525/2620/4525/4620 REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2525/2620/4525/4620 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F4620 010 = PIC18F4525 100 = PIC18F2620 110 = PIC18F2525 bit 4-0 REV4:REV0: Revision ID bits These bits are used to i
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PIC18F2525/2620/4525/4620 23.2 Watchdog Timer (WDT) For PIC18F2525/2620/4525/4620 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
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PIC18F2525/2620/4525/4620 REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configurati
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PIC18F2525/2620/4525/4620 23.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available.
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PIC18F2525/2620/4525/4620 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
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PIC18F2525/2620/4525/4620 FIGURE 23-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 23.4.3 CM Test CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
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PIC18F2525/2620/4525/4620 23.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes.
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PIC18F2525/2620/4525/4620 23.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s.
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PIC18F2525/2620/4525/4620 FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. TABLAT register returns a value of ‘0’.
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PIC18F2525/2620/4525/4620 23.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 23.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
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PIC18F2525/2620/4525/4620 24.0 INSTRUCTION SET SUMMARY PIC18F2525/2620/4525/4620 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 24.
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PIC18F2525/2620/4525/4620 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
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PIC18F2525/2620/4525/4620 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
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PIC18F2525/2620/4525/4620 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f
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PIC18F2525/2620/4525/4620 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
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PIC18F2525/2620/4525/4620 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtr
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PIC18F2525/2620/4525/4620 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
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PIC18F2525/2620/4525/4620 ADDWFC ADD W and Carry bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Operation: (W) + (f) + (C) → dest Status Affected: N, Z Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: f {,d {,a}} Encoding: 00da ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F2525/2620/4525/4620 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F2525/2620/4525/4620 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f, b {,a} Operation: 0 → f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F2525/2620/4525/4620 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0011 nnnn nnnn Encoding: 1110 If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
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PIC18F2525/2620/4525/4620 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
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PIC18F2525/2620/4525/4620 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] n Operation: (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
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PIC18F2525/2620/4525/4620 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
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PIC18F2525/2620/4525/4620 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
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PIC18F2525/2620/4525/4620 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
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PIC18F2525/2620/4525/4620 CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f, 1→Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 24.2.
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PIC18F2525/2620/4525/4620 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) → dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F2525/2620/4525/4620 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the cont
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PIC18F2525/2620/4525/4620 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then, (W<7:4>) + 6 + DC → W<7:4> ; else, (W<7:4>) + DC → W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 0000 DAW adjusts the eight-bit
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PIC18F2525/2620/4525/4620 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F2525/2620/4525/4620 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No o
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PIC18F2525/2620/4525/4620 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
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PIC18F2525/2620/4525/4620 IORLW Inclusive OR Literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
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PIC18F2525/2620/4525/4620 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
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PIC18F2525/2620/4525/4620 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR Operation: (fs) → fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
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PIC18F2525/2620/4525/4620 MOVLW Move Literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) → f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
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PIC18F2525/2620/4525/4620 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) x k → PRODH:PRODL 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) x (f) → PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
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PIC18F2525/2620/4525/4620 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: None Operation: (f)+1→f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
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PIC18F2525/2620/4525/4620 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
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PIC18F2525/2620/4525/4620 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
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PIC18F2525/2620/4525/4620 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q2 Q3 Q4 Decode No operation No operation POP P
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PIC18F2525/2620/4525/4620 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
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PIC18F2525/2620/4525/4620 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
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PIC18F2525/2620/4525/4620 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Operation: (f) → dest, (f<0>) → dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F2525/2620/4525/4620 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
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PIC18F2525/2620/4525/4620 SUBLW Subtract W from Literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
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PIC18F2525/2620/4525/4620 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
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PIC18F2525/2620/4525/4620 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT Example 2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Ins
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PIC18F2525/2620/4525/4620 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, (TABLAT) → Holding Register Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = F
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PIC18F2525/2620/4525/4620 TSTFSZ Test f, Skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR Literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
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PIC18F2525/2620/4525/4620 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F2525/2620/4525/4620 24.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 24-1 (page 268) apply to both the standard and extended PIC18 instruction sets.
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PIC18F2525/2620/4525/4620 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: FSR(f) + k → FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k → FSR2, Operation: (TOS) → PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
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PIC18F2525/2620/4525/4620 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
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PIC18F2525/2620/4525/4620 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: ((FSR2) + zs) → ((FSR2) + zd) Operation: k → (FSR2), FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
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PIC18F2525/2620/4525/4620 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: Operation: FSR(f – k) → FSR(f) Status Affected: None Encoding: 1110 FSR2 – k → FSR2, (TOS) → PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
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PIC18F2525/2620/4525/4620 24.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.5.1 “Indexed Addressing with Literal Offset”).
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PIC18F2525/2620/4525/4620 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] Operands: 0 ≤ f ≤ 95 0≤b≤7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by t
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PIC18F2525/2620/4525/4620 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2525/2620/4525/4620 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
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PIC18F2525/2620/4525/4620 25.
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PIC18F2525/2620/4525/4620 25.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC18F2525/2620/4525/4620 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC18F2525/2620/4525/4620 25.11 PICSTART Plus Development Programmer 25.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC18F2525/2620/4525/4620 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) .............................................
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PIC18F2525/2620/4525/4620 FIGURE 26-1: PIC18F2525/2620/4525/4620 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2X2X/4X2X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 26-2: PIC18F2525/2620/4525/4620 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F2X2X/4X2X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency DS39626E-page 322 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 26-3: PIC18LF2525/2620/4525/4620 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF2X2X/4X2X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 26.1 DC Characteristics: Supply Voltage PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2525/2620/4525/4620 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
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PIC18F2525/2620/4525/4620 26.3 DC Characteristics: PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.
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PIC18F2525/2620/4525/4620 26.3 DC Characteristics: PIC18F2525/2620/4525/4620 (Industrial) PIC18LF2525/2620/4525/4620 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.
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PIC18F2525/2620/4525/4620 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Data EEPROM Memory D120 ED Byte Endurance 100K 1M — D121 VDRW VDD for Read/Write VMIN — 5.
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PIC18F2525/2620/4525/4620 TABLE 26-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
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PIC18F2525/2620/4525/4620 FIGURE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared in software) VLVD (HLVDIF set by hardware) HLVDIF(1) Note 1: VDIRMAG = 0. TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym No. D420 Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL = 0000 Transition High-to-Low HLVDL = 0001 2.06 2.17 2.28 V 2.12 2.
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PIC18F2525/2620/4525/4620 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
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PIC18F2525/2620/4525/4620 26.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-5 specifies the load conditions for the timing specifications.
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PIC18F2525/2620/4525/4620 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-6: Param. No.
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PIC18F2525/2620/4525/4620 TABLE 26-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25°C unless otherwise stated.
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PIC18F2525/2620/4525/4620 FIGURE 26-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 26-5 for load conditions. TABLE 26-9: Param No.
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PIC18F2525/2620/4525/4620 FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 26-5 for load conditions.
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PIC18F2525/2620/4525/4620 FIGURE 26-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 26-5 for load conditions. TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period No prescaler With prescaler No prescaler With prescaler 45 Tt1H 47 — ns 10 — ns 0.
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PIC18F2525/2620/4525/4620 FIGURE 26-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 26-5 for load conditions. TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TccL TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With PIC18FXXXX prescaler PIC18LFXXXX 0.5 TCY + 20 — ns 10 — ns 20 — ns CCPx Input High Time 0.
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PIC18F2525/2620/4525/4620 FIGURE 26-12: PARALLEL SLAVE PORT TIMING (PIC18F4525/4620) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 26-5 for load conditions. TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4525/4620) Param. No.
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PIC18F2525/2620/4525/4620 FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 26-5 for load conditions. TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units 70 TssL2scH, TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input 71 TscH SCK Input High Time (Slave mode) Continuous 1.
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PIC18F2525/2620/4525/4620 FIGURE 26-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 26-5 for load conditions. TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol TscH 71A 72 TscL 72A Characteristic Min Max Units SCK Input High Time (Slave mode) Continuous 1.
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PIC18F2525/2620/4525/4620 FIGURE 26-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI 73 Note: bit 6 - - - -1 LSb In 74 Refer to Figure 26-5 for load conditions. © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input TssL2scL 71 TscH 71A 72 TscL 72A Min Max Units Conditions 3 TCY — ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.
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PIC18F2525/2620/4525/4620 FIGURE 26-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In Note: 77 bit 6 - - - -1 LSb In 74 Refer to Figure 26-5 for load conditions. TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
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PIC18F2525/2620/4525/4620 I2C™ BUS START/STOP BITS TIMING FIGURE 26-17: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-5 for load conditions. TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
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PIC18F2525/2620/4525/4620 TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH 101 91 106 107 92 109 110 2: — μs μs — — 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs MSSP module 1.5 TCY — — 1000 ns 20 + 0.1 CB 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.
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PIC18F2525/2620/4525/4620 MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 26-19: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-5 for load conditions. TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
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PIC18F2525/2620/4525/4620 TABLE 26-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
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PIC18F2525/2620/4525/4620 FIGURE 26-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 26-5 for load conditions. TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
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PIC18F2525/2620/4525/4620 FIGURE 26-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure 26-5 for load conditions. TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No.
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PIC18F2525/2620/4525/4620 FIGURE 26-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 (1) 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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PIC18F2525/2620/4525/4620 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
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PIC18F2525/2620/4525/4620 FIGURE 27-2: TYPICAL IPD vs. VDD ACROSS TEMPERATURE (SLEEP MODE) 100 10 IPD (uA) 125C 85C 1 25C 0.1 -40C 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-3: MAXIMUM IPD vs. VDD ACROSS TEMPERATURE (SLEEP MODE) 100 125C 10 IPD (uA) 85C 1 25C -40C 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39626E-page 362 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-4: TYPICAL T1OSC DELTA CURRENT vs. VDD ACROSS TEMP. (DEVICE IN SLEEP, T1OSC IN LOW-POWER MODE) p 3.0 2.5 2.0 IPD (uA) 85C 1.5 25C 1.0 -10C 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-5: MAXIMUM T1OSC DELTA CURRENT vs. VDD ACROSS TEMP. (DEVICE IN SLEEP, TIOSC IN LOW-POWER MODE) 4 3 85C IPD (uA) 25C -10C 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-6: TYPICAL T1OSC DELTA CURRENT vs. VDD ACROSS TEMP. (DEVICE IN SLEEP, T1OSC IN HIGH-POWER MODE) 16 14 12 IPD (uA) 10 8 85C 25C 6 -40C 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-7: MAXIMUM T1OSC DELTA CURRENT vs. VDD ACROSS TEMP. (DEVICE IN SLEEP, T1OSC IN HIGH-POWER MODE) 30 25 IPD (uA) 20 15 85C 10 25C -40C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39626E-page 364 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-8: TYPICAL BOR DELTA CURRENT vs. VDD ACROSS TEMP. (BORV = 2.7V, SLEEP MODE) 55.00 50.00 Device Held in RESET MAX (125C) 45.00 MAX (85C) 40.00 IPD (uA) TYP (25C) 35.00 MIN (-40C) 30.00 Device in SLEEP 25.00 20.00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-9: TYPICAL WDT CURRENT vs. VDD ACROSS TEMPERATURE (WDT DELTA CURRENT IN SLEEP MODE) 6.00 5.00 85C 125C 25C IPD (uA) 4.00 -40C 3.00 2.00 1.00 0.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-10: MAXIMUM WDT CURRENT vs. VDD ACROSS TEMPERATURE (WDT DELTA CURRENT IN SLEEP MODE) 12.0 10.0 125C 8.0 IPD (uA) 85C 6.0 25C -40C 4.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39626E-page 366 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-11: TYPICAL IDD ACROSS VDD (RC_RUN MODE, 25°C) 10 (4.2V 8 MHz IDD (mA) 4 MHz 2 MHz 1 MHz 1 500 kHz 250 kHz 125 kHz 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-12: MAXIMUM IDD ACROSS VDD (RC_RUN MODE, 85°C) 10 8 MHz (4.2V IDD (mA) 4 MHz 2 MHz 1 MHz 1 500 kHz 250 kHz 125 kHz 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-13: TYPICAL AND MAXIMUM IDD ACROSS VDD (RC_RUN MODE, 31 kHz) IDD (uA) 1000 Maximum (-40C) 100 Typical (25C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-14: TYPICAL IDD ACROSS VDD (RC_IDLE MODE, 25°C) 10 (4.2V) 8 MHz 1 4 MHz IDD (mA) 2 MHz 1 MHz 250 kHz 500 kHz 125 kHz 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39626E-page 368 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-15: MAXIMUM IDD ACROSS VDD (RC_IDLE MODE, -40°C-85°C) 10 (4.2V IDD (mA) 8 MHz 4 MHz 1 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-16: TYPICAL AND MAXIMUM IDD ACROSS VDD (RC_IDLE MODE, 31 kHz) 25 20 IDD (uA) 15 Maximum (85C) 10 Typical (25C) 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-17: TYPICAL AND MAXIMUM SEC_RUN CURRENT vs. VDD ACROSS TEMPERATURE (T1OSC IN LOW-POWER MODE) 140.0 120.0 Max (-10C) 100.0 IDD (uA) 80.0 60.0 Typ (85C) Typ (25C) Typ (-10C) 40.0 20.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-18: TYPICAL AND MAXIMUM SEC_IDLE CURRENT vs. VDD ACROSS TEMPERATURE (T1OSC IN LOW-POWER MODE) 14.0 12.0 Typ (25C) 10.0 Max (85C) IDD (uA) 8.0 Typ (85C) 6.0 Typ (-10C) 4.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.
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PIC18F2525/2620/4525/4620 FIGURE 27-19: TYPICAL IDD vs. FOSC, 500 kHz TO 4 MHz (PRI_RUN MODE (EC CLOCK), 25°C) 3.0 2.5 5.5V 5.0V 2.0 IDD (mA) 4.5V 4.0V 1.5 3.5V 3.0V 1.0 2.5V 2.0V 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Fosc (MHz) FIGURE 27-20: MAXIMUM IDD vs. FOSC, 500 kHz TO 4 MHz (PRI_RUN MODE (EC CLOCK), -40°C TO +125°C) 4.5 5.5V IDD (mA) 4.0 3.5 5.0V 3.0 4.5V 2.5 4.0V 2.0 3.5V 1.5 3.0V 1.0 2.5V 2.0V 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
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PIC18F2525/2620/4525/4620 FIGURE 27-21: TYPICAL IDD vs. FOSC _ , 4 MHz TO ( 40 MHz ) (PRI_RUN MODE (EC CLOCK), 25°C) 20 5.5V 18 5.0V 16 4.5V 14 IDD (mA) 12 4.0V 10 8 3.5V 6 3.0V 4 2 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc (MHz) FIGURE 27-22: MAXIMUM IDD vs. FOSC, 4 MHz TO 40 MHz (PRI_RUN MODE (EC CLOCK), -40°C TO +125°C) 24 22 5.5V 20 5.0V 18 4.5V 16 IDD (mA) 14 4.0V 12 10 3.5V 8 6 3.0V 4 2.5V 2 2.
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PIC18F2525/2620/4525/4620 FIGURE 27-23: TYPICAL IDD vs. FOSC, HS/PLL (PRI_RUN MODE, 25°C) 24 22 20 18 5.5V IDD (mA) 16 5.0V 14 4.5V 12 4.2V 10 8 6 4 16 18 20 22 24 26 28 30 32 34 36 38 40 36 38 40 Fosc (MHz) FIGURE 27-24: MAXIMUM IDD vs. FOSC, HS/PLL (PRI_RUN MODE, -40°C) 24 22 20 5.5V 18 5.0V IDD (mA) 16 4.5V 14 4.2V 12 10 8 6 4 16 18 20 22 24 26 28 30 32 34 Fosc (MHz) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-25: TYPICAL IDD vs. FOSC, 500 kHz TO 4 MHz (PRI_IDLE MODE, 25°C) 1.1 1.0 0.9 5.5V 0.8 5.0V 0.7 IDD (mA) 4.5V 0.6 4.0V 0.5 3.5V 0.4 3.0V 0.3 2.5V 2.0V 0.2 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Fosc (MHz) FIGURE 27-26: MAXIMUM IDD vs. FOSC, 500 kHz TO 4 MHz (PRI_IDLE MODE, -40°C TO +125°C) 1.2 1.1 1.0 5.5V 0.9 5.0V 0.8 4.5V IDD (mA) 0.7 4.0V 0.6 3.5V 0.5 3.0V 0.4 2.5V 0.3 2.0V 0.2 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
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PIC18F2525/2620/4525/4620 FIGURE 27-27: TYPICAL IDD vs. FOSC, 4 MHz TO 40 MHz (PRI_IDLE MODE, 25°C) 12 11 IDD (mA) 10 9 5.5V 8 5.0V 7 4.5V 6 4.0V 5 4 3.5V 3 3.0V 2 1 2.5V 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Fosc (MHz) FIGURE 27-28: MAXIMUM IDD vs. FOSC, 4 MHz TO 40 MHz (PRI_IDLE MODE, -40°C TO +125°C) 12 11 10 5.5V 9 5.0V 8 4.5V IDD (mA) 7 6 4.0V 5 3.5V 4 3 3.0V 2 1 2.5V 2.
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PIC18F2525/2620/4525/4620 FIGURE 27-29: TYPICAL IDD vs. FOSC, HS/PLL (PRI_IDLE MODE, 25°C) 12 11 10 9 8 5.5V IDD (mA) 7 5.0V 6 4.5V 4.2V 5 4 3 2 1 0 16 18 20 22 24 26 28 30 32 34 36 38 40 36 38 40 Fosc (MHz) FIGURE 27-30: MAXIMUM IDD vs. FOSC, HS/PLL (PRI_IDLE MODE, -40°C) 12 11 10 9 5.5 8 5.0 IDD (mA) 7 4.5 6 4.2 5 4 3 2 1 0 16 18 20 22 24 26 28 30 32 34 Fosc (MHz) DS39626E-page 376 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-31: VIN (ST) vs. VDD, 25°C (-40°C TO +125°C) 4.0 3.5 VIH Min (-40C) VIH Typ (25C) 3.0 VIH Max (125C) VIN (V) 2.5 2.0 1.5 1.0 VIL Min (125C) 0.5 VIL Max (-40C) VIL Typ (25C) 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5 5.0 5.5 VDD (V) FIGURE 27-32: VIN (TTL) vs. VDD, 25°C (-40°C TO +125°C) 1.6 VIH Max (-40C) 1.4 VIH Typ (25C) VIH Min (125C) 1.2 VIN (V) 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-33: VOL vs. IOL (VDD = 3.0V, -40°C TO +85°C) ) ( 2.0 1.8 1.6 1.4 Max (85C) VOL (V) 1.2 1.0 0.8 Typ (25C) 0.6 0.4 Min (-40C) 0.2 0.0 0 5 10 15 20 25 20 25 IOL (-ma) FIGURE 27-34: VOL vs. IOL (VDD = 5.0V, -40°C TO +125°C) 2.0 1.8 1.6 1.4 VOL (V) 1.2 1.0 0.8 Max (85C) 0.6 Typ (25C) 0.4 0.2 Min (-40C) 0.0 0 5 10 15 IOL (-ma) DS39626E-page 378 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-35: VOH vs. IOH (VDD = 3.0V, -40°C TO +85°C) 3.0 2.5 2.0 VOH (V) Max (-40C) 1.5 Min (85C) Typ (25C) 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-ma) FIGURE 27-36: VOH vs. IOH (VDD = 5.0V, -40°C TO +125°C) 5.0 4.5 Max (-40C) 4.0 3.5 Typ (25C) VOH (V) 3.0 2.5 Min (125C) 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-ma) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 FIGURE 27-37: INTOSC FREQUENCY( vs. ,VDD,, TEMPERATURE (-40°C, +25°C, +85°C, +125°C) , ) 8.4 Max Freq 8.3 8.2 125C Typ 85C Typ Freq (MHz) 8.1 25C Typ 8.0 -40C Typ 7.9 7.8 Min Freq 7.7 7.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-38: INTRC vs. VDD ACROSS TEMPERATURE (-40°C TO +125°C) 40 39 38 Max (125C) 37 36 35 Freq (kHz) 34 Max (-40C) 33 32 31 Typ (25C) 30 29 Min (85C) 28 27 Min (125C) 26 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC18F2525/2620/4525/4620 FIGURE 27-39: WDT PERIOD vs. VDD ACROSS TEMPERATURE (1:1 POSTSCALER, -40°C TO +125°C) 4.6 Longest 4.4 4.2 Shortest (125C) Shortest (85C) Typical (25C) Period (ms) 4.0 3.8 3.6 3.4 3.2 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SPDIP Example PIC18F2620-I/SP e3 0810017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
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PIC18F2525/2620/4525/4620 28.1 Package Marking Information (Continued) 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39626E-page 384 Example PIC18F4620 -I/ML e3 0810017 Example PIC18F4620 -I/PT e3 0810017 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 28.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
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PIC18F2525/2620/4525/4620 # # $ % &'( # ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 L1 6 &! ' ! 9 ' &! 7"') % ! β 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& .
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PIC18F2525/2620/4525/4620 * + ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
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PIC18F2525/2620/4525/4620 ** , - % ! . / 0 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & < & # %% , & & 4 !! - : > #& . .
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PIC18F2525/2620/4525/4620 ** , - % ! . / 0 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 ** 12 ! " , - 3 1 4 04 04 % ' 1,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 6 &! ' ! 9 ' &! 7"') % 9 #! A2 L1 99 . .
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PIC18F2525/2620/4525/4620 ** 12 ! " , - 3 1 4 04 04 % ' 1,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 APPENDIX A: REVISION HISTORY Revision A (April 2004) Original data sheet for PIC18F2525/2620/4525/4620 devices. Revision B (June 2004) This revision introduces High/Low-Voltage Detect updates to Section 22.0 and includes minor corrections to the data sheet text related to the High/Low-Voltage Detect update. Revision C (January 2007) Revision D (November 2007) Updated values in “Power-Down and Supply Current” tables in Section 26.
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PIC18F2525/2620/4525/4620 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1.
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PIC18F2525/2620/4525/4620 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable © 2008 Microchip Technology Inc.
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PIC18F2525/2620/4525/4620 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the Enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to Enhanced device migrations.
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PIC18F2525/2620/4525/4620 INDEX A A/D ................................................................................... 223 A/D Converter Interrupt, Configuring ....................... 227 Acquisition Requirements ........................................ 228 ADCON0 Register .................................................... 223 ADCON1 Register .................................................... 223 ADCON2 Register .................................................... 223 ADRESH Register ................
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PIC18F2525/2620/4525/4620 C C Compilers MPLAB C18 ............................................................. 318 MPLAB C30 ............................................................. 318 CALL ................................................................................ 282 CALLW ............................................................................. 311 Capture (CCP Module) ..................................................... 141 Associated Registers ..........................................
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PIC18F2525/2620/4525/4620 DC Characteristics ........................................................... 335 Power-Down and Supply Current ............................ 325 Supply Voltage ......................................................... 324 DCFSNZ .......................................................................... 287 DECF ............................................................................... 286 DECFSZ ...........................................................................
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PIC18F2525/2620/4525/4620 High/Low-Voltage Detect ................................................. 243 Applications .............................................................. 246 Associated Registers ............................................... 247 Characteristics ......................................................... 339 Current Consumption ............................................... 245 Effects of a Reset ..................................................... 247 Operation ..................
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PIC18F2525/2620/4525/4620 SLEEP ..................................................................... 302 SUBFWB .................................................................. 302 SUBLW .................................................................... 303 SUBWF .................................................................... 303 SUBWFB .................................................................. 304 SWAPF .................................................................... 304 TBLRD .......
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PIC18F2525/2620/4525/4620 RA3/AN3/VREF+ ................................................... 13, 17 RA4/T0CKI/C1OUT .............................................. 13, 17 RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17 RB0/INT0/FLT0/AN12 .......................................... 14, 18 RB1/INT1/AN10 ................................................... 14, 18 RB2/INT2/AN8 ..................................................... 14, 18 RB3/AN9/CCP2 ...................................................
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PIC18F2525/2620/4525/4620 PWM (CCP Module) Associated Registers ............................................... 146 Auto-Shutdown (CCP1 Only) ................................... 145 Duty Cycle ................................................................ 144 Example Frequencies/Resolutions .......................... 145 Operation Setup ....................................................... 145 Period ....................................................................... 144 TMR2 to PR2 Match ..........
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PIC18F2525/2620/4525/4620 Sleep OSC1 and OSC2 Pin States ...................................... 31 Software Simulator (MPLAB SIM) .................................... 318 Special Event Trigger. See Compare (ECCP Mode). Special Event Trigger. See Compare (ECCP Module). Special Features of the CPU ............................................ 249 Special Function Registers ................................................ 62 Map ............................................................................
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PIC18F2525/2620/4525/4620 First Start Bit Timing ................................................ 189 Full-Bridge PWM Output .......................................... 153 Half-Bridge PWM Output ......................................... 152 High/Low-Voltage Detect Characteristics ................ 339 High-Voltage Detect Operation (VDIRMAG = 1) ...... 246 I2C Bus Data ............................................................ 354 I2C Bus Start/Stop Bits .............................................
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PIC18F2525/2620/4525/4620 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F2525/2620/4525/4620 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F2525/2620/4525/4620 PIC18F2525/2620/4525/4620 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2525/2620(1), PIC18F4525/4620(1), PIC18F2525/2620T(2), PIC18F4525/4620T(2); VDD range 4.2V to 5.5V PIC18LF2525/2620(1), PIC18LF4525/4620(1), PIC18LF2525/2620T(2), PIC18LF4525/4620T(2); VDD range 2.0V to 5.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.