Datasheet

© 2009 Microchip Technology Inc. DS39636D-page 69
PIC18F2X1X/4X1X
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53, 197
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53, 197
RCREG EUSART Receive Register 0000 0000 53, 204
TXREG EUSART Transmit Register 0000 0000 53, 202
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 194
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 53, 195
IPR2 OSCFIP CMIP
— — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 54, 93
PIR2 OSCFIF CMIF
— — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 54, 89
PIE2 OSCFIE CMIE
— — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 54, 91
IPR1 PSPIP
(2)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 54, 92
PIR1 PSPIF
(2)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 54, 88
PIE1 PSPIE
(2)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54, 90
OSCTUNE INTSRC PLLEN
(3)
— TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 29, 54
TRISE
(2)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 54, 110
TRISD
(2)
PORTD Data Direction Control Register 1111 1111 54, 106
TRISC PORTC Data Direction Control Register 1111 1111 54, 103
TRISB PORTB Data Direction Control Register 1111 1111 54, 100
TRISA TRISA7
(5)
TRISA6
(5)
Data Direction Control Register for PORTA 1111 1111 54, 97
LATE
(2)
— — — — — PORTE Data Latch Register
(Read and Write to Data Latch)
---- -xxx 54, 109
LATD
(2)
PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 106
LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 103
LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 100
LATA LATA7
(6)
LATA6
(6)
PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 97
PORTE
— — — —RE3
(4)
RE2
(2)
RE1
(2)
RE0
(2)
---- xxxx 54, 109
PORTD
(2)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 54, 106
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 54, 103
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 100
PORTA RA7
(5)
RA6
(5)
RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 54, 97
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as
‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as
‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: Bit 7 and bit 6 are cleared by user software or by a POR.