Datasheet

PIC18F2X1X/4X1X
DS39636D-page 68 © 2009 Microchip Technology Inc.
TMR0H Timer0 Register High Byte 0000 0000 52, 117
TMR0L Timer0 Register Low Byte xxxx xxxx 52, 117
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 52, 115
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 32, 52
HLVDCON VDIRMAG
— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 52, 233
WDTCON
— — — — — — —SWDTEN--- ---0 52, 249
RCON IPEN SBOREN
(1)
—RITO PD POR BOR 0q-1 11q0 44, 50, 94
TMR1H Timer1 Register High Byte xxxx xxxx 52, 123
TMR1L Timer1 Register Low Bytes xxxx xxxx 52, 123
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 52, 119
TMR2 Timer2 Register 0000 0000 52, 126
PR2 Timer2 Period Register 1111 1111 52, 126
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 125
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 52, 161,
162
SSPADD SSP Address Register in I
2
C Slave mode. SSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 52, 162
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 52, 154,
163
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 155,
164
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 52, 165
ADRESH A/D Result Register High Byte xxxx xxxx 53, 222
ADRESL A/D Result Register Low Byte xxxx xxxx 53, 222
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 53, 213
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 53, 214
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 53, 215
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 53, 132
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 53, 132
CCP1CON P1M1
(2)
P1M0
(2)
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 131,
139
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 53, 132
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 53, 132
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 53, 131
BAUDCON ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 53, 196
PWM1CON PRSEN PDC6
(2)
PDC5
(2)
PDC4
(2)
PDC3
(2)
PDC2
(2)
PDC1
(2)
PDC0
(2)
0000 0000 53, 148
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1
(2)
PSSBD0
(2)
0000 0000 53, 149
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 229
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 53, 223
TMR3H Timer3 Register High Byte xxxx xxxx 53, 129
TMR3L Timer3 Register Low Byte xxxx xxxx 53, 129
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 53, 127
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as
‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as
‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as
‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: Bit 7 and bit 6 are cleared by user software or by a POR.