Datasheet

PIC18F2X1X/4X1X
DS39636D-page 348 © 2009 Microchip Technology Inc.
FIGURE 25-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 25-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 25-22: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 25-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 25-5 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 25-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns