Datasheet

PIC18F2X1X/4X1X
DS39636D-page 222 © 2009 Microchip Technology Inc.
18.8 Use of the CCP2 Trigger
An A/D conversion can be started by the special event
trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE
bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
ACQ time selected before the special event trigger sets
the GO/DONE
bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
special event trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2
OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54
ADRESH A/D Result Register, High Byte 53
ADRESL A/D Result Register, Low Byte 53
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 53
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 53
PORTA RA7
(1)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 54
TRISA TRISA7
(2)
TRISA6
(2)
PORTA Data Direction Control Register 54
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54
TRISB PORTB Data Direction Control Register 54
LATB PORTB Data Latch Register (Read and Write to Data Latch) 54
PORTE
(4)
— — — —RE3
(3)
RE2 RE1 RE0 54
TRISE
(4)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54
LATE
(4)
— — — — — PORTE Data Latch Register 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers are not implemented on 28-pin devices.