Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 462  2010-2012 Microchip Technology Inc.
TABLE 27-19: MASTER SSP I
2
C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
100 THIGH
Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
101 T
LOW
Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
102 T
R
SDA and SCL
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from
10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(1)
— 300 ns
103 T
F
SDA and SCL
Fall Time
100 kHz mode — 300 ns CB is specified to be
from
10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(1)
— 100 ns
90 T
SU:STA
Start Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Repeated Start
condition
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
91 T
HD:STA
Start Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
clock pulse is generated
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
106 T
HD:DAT
Data Input
Hold Time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
107 TSU:DAT
Data Input
Setup Time
100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO
Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
109 T
AA
Output Valid
from Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode
(1)
——ns
110 T
BUF
Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be
free before a new trans-
mission can start
400 kHz mode 1.3 — ms
D102 C
B
Bus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
2: A fast mode I
2
C bus device can be used in a standard mode I
2
C bus system, but parameter 107  250 ns
must then be met. This will automatically be the case if the device does not stretch the Low period of the
SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit
to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.