Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 360  2010-2012 Microchip Technology Inc.
REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed x = Bit is unknown
bit 7 MCLRE: MCLR
Pin Enable bit
1 = MCLR
pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR
disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 P2BMX: P2B Input MUX bit
1 = P2B is on RB5
(1)
P2B is on RD2
(2)
0 = P2B is on RC0
bit 4 T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5
bit 3 HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize
0 = The system clock is held off until the HFINTOSC is stable
bit 2 CCP3MX: CCP3 MUX bit
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RC6
(1)
CCP3 input/output is multiplexed with RE0
(2)
bit 1 PBADEN: PORTB A/D Enable bit
1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset
0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset
bit 0 CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Note 1: PIC18(L)F2XK22 devices only.
2: PIC18(L)F4XK22 devices only.