Datasheet

 2010 Microchip Technology Inc. DS41303G-page 241
PIC18F2XK20/4XK20
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR1 PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 62
PIE1
PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 62
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 62
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 61
TXREG
EUSART Transmit Register 61
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 61
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 61
SPBRGH EUSART Baud Rate Generator Register, High Byte 61
SPBRG EUSART Baud Rate Generator Register, Low Byte 61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin