Datasheet

PIC18F45J10 FAMILY
DS39682E-page 84 © 2009 Microchip Technology Inc.
FIGURE 9-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC
TMR0IE
GIE/GIEH
PEIE/GIEL
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
PEIE/GIEL
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
Idle or Sleep modes
GIE/GIEH
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
IPEN