Datasheet

PIC18F45J10 FAMILY
DS39682E-page 50 © 2009 Microchip Technology Inc.
TRISE PIC18F2XJ10 PIC18F4XJ10 0000 -111 1111 -111 uuuu -uuu
TRISD
PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu
TRISA PIC18F2XJ10 PIC18F4XJ10 --1- 1111 --1- 1111 --u- uuuu
SSP2BUF PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
LATE
PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu
LATD
PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
LATA PIC18F2XJ10 PIC18F4XJ10 --xx xxxx --uu uuuu --uu uuuu
SSP2ADD
PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu
SSP2STAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu
SSP2CON1
PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu
PORTE PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu
PORTD
PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA PIC18F2XJ10 PIC18F4XJ10 --0- 0000 --0- 0000 --u- uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.