Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 37
PIC18F45J10 FAMILY
4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes, while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-2), the primary oscillator is shut down and the
OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-3). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
FIGURE 4-2: TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTRC
Q1
PC + 4
Q2
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.
SCS<1:0> bits Changed
OSTS bit Set
TOST
(1)