Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 333
PIC18F45J10 FAMILY
FIGURE 24-18: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 24-19: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid 40 ns
121 TCKRF Clock Out Rise Time and Fall Time (Master mode) 20 ns
122 TDTRF Data Out Rise Time and Fall Time 20 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CK (DT hold time) 10 ns
126 TCKL2DTL Data Hold after CK (DT hold time) 15 ns
121
121
120
122
TX/CK
RX/DT
pin
pin
Note: Refer to Figure 24-3 for load conditions.
125
126
TX/CK
RX/DT
pin
pin
Note: Refer to Figure 24-3 for load conditions.