Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 331
PIC18F45J10 FAMILY
FIGURE 24-16: MASTER SSP I
2
C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 24-20: MASTER SSP I
2
C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 24-17: MASTER SSP I
2
C™ BUS DATA TIMING
Param.
No.
Symbol Characteristic Min Max Units Conditions
90 T
SU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated Start
condition
Setup Time 400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
91 T
HD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
Hold Time 400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
92 T
SU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
93 T
HD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C™ pins.
Note: Refer to Figure 24-3 for load conditions.
91
93
SCLx
SDAx
Start
Condition
Stop
Condition
90
92
Note: Refer to Figure 24-3 for load conditions.
90
91 92
100
101
103
106
107
109
109
110
102
SCLx
SDAx
In
SDAx
Out