Datasheet

PIC18F45J10 FAMILY
DS39682E-page 324 © 2009 Microchip Technology Inc.
FIGURE 24-9: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)
TABLE 24-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)
TABLE 24-13: PARALLEL SLAVE PORT REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
50 T
CCL CCPx Input Low
Time
No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
51 TCCH CCPx Input
High Time
No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
52 T
CCP CCPx Input Period 3 TCY + 40
N
— ns N = prescale
value (1, 4 or 16)
53 T
CCR CCPx Output Fall Time — 25 ns
54 TCCF CCPx Output Fall Time — 25 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data In Valid before WR
↑ or CS ↑ (setup time) 20 — ns
63 TwrH2dtI WR
↑ or CS ↑ to Data–In Invalid (hold time) 20 — ns
64 TrdL2dtV RD
↓ and CS ↓ to Data–Out Valid — 80 ns
65 TrdH2dtI RD
↑ or CS ↓ to Data–Out Invalid 10 30 ns
66 TibfINH Inhibit of the IBF Flag bit being Cleared from
WR
↑ or CS ↑
—3 T
CY
Note: Refer to Figure 24-3 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53
54
(Compare or PWM Mode)