Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 321
PIC18F45J10 FAMILY
FIGURE 24-5: CLKO AND I/O TIMING
TABLE 24-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
10 T
OSH2CKLOSC1 ↑ to CLKO ↓ — 75 200ns
11 TOSH2CKHOSC1 ↑ to CLKO ↑ — 75 200ns
12 T
CKR CLKO Rise Time — 15 30 ns
13 TCKF CLKO Fall Time — 15 30 ns
14 TCKL2IOVCLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns
15 T
IOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns
16 TCKH2IOI Port In Hold after CLKO ↑ 0——ns
17 TOSH2IOVOSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 T
OSH2IOIOSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
100 — — ns
18A 200 — — ns
19 T
IOV2OSH Port Input Valid to OSC1 ↑
(I/O in setup time)
0——ns
20 T
IOR Port Output Rise Time — — 6 ns
21 TIOF Port Output Fall Time — — 5 ns
22† T
INP INTx pin High or Low Time TCY ——ns
23† TRBP RB<7:4> Change INTx High or Low Time TCY ——ns
† These parameters are asynchronous events not related to any internal clock edges.
Note: Refer to Figure 24-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value