Datasheet

© 2009 Microchip Technology Inc. DS39682E-page 131
PIC18F45J10 FAMILY
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
RCON IPEN
— CM RI TO PD POR BOR 46
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49
PIR2
OSCFIF CMIF — — BCL1IF — — CCP2IF 49
PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49
IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49
TRISB PORTB Data Direction Control Register 50
TRISC PORTC Data Direction Control Register 50
TMR1L Timer1 Register Low Byte 48
TMR1H Timer1 Register High Byte 48
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 48
CCPR1L Capture/Compare/PWM Register 1 Low Byte 49
CCPR1H Capture/Compare/PWM Register 1 High Byte 49
CCP1CON
P1M1
(1)
P1M0
(1)
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49
CCPR2L Capture/Compare/PWM Register 2 Low Byte 49
CCPR2H Capture/Compare/PWM Register 2 High Byte 49
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.