Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 56 Preliminary © 2007 Microchip Technology Inc.
RXF1EIDL 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
RXF1EIDH 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
RXF1SIDL 2585 2680 4585 4680 xxx- x-xx uuu- u-uu uuu- u-uu
RXF1SIDH 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0EIDL 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0EIDH 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
RXF0SIDL 2585 2680 4585 4680 xxx- x-xx uuu- u-uu uuu- u-uu
RXF0SIDH 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D7
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D6
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D5
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D4
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D3
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D2
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D1
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5D0
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5DLC
(6)
2585 2680 4585 4680 -xxx xxxx -uuu uuuu -uuu uuuu
B5EIDL
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5EIDH
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B5SIDL
(6)
2585 2680 4585 4680 xxxx x-xx uuuu u-uu uuuu u-uu
B5SIDH
(6)
2585 2680 4585 4680 xxxx x-xx uuuu u-uu uuuu u-uu
B5CON
(6)
2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuu
B4D7
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D6
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D5
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D4
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D3
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D2
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D1
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4D0
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
B4DLC
(6)
2585 2680 4585 4680 -xxx xxxx -uuu uuuu -uuu uuuu
B4EIDL
(6)
2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.