Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 47
PIC18F2585/2680/4585/4680
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR
TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
T
PWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
T
PLL ≈ 2 ms max. First three stages of the PWRT timer.