Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 441
PIC18F2585/2680/4585/4680
FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 27-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns V
DD = 2.0V
76 T
DOF SDO Data Output Fall Time — 25 ns
78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns V
DD = 2.0V
79 TSCF SCK Output Fall Time — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after
SCK Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX 100 ns V
DD = 2.0V
81 T
DOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns