Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 440 Preliminary © 2007 Microchip Technology Inc.
FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In
LSb In
bit 6 - - - -1
Note: Refer to Figure 27-4 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
76 T
DOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
79 T
SCF SCK Output Fall Time — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after
SCK Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V