Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 353
PIC18F2585/2680/4585/4680
REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
(1)
bit 7 bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ -n = Value at POR
Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset
Values
on page
RCON
IPEN SBOREN — RI TO PD POR BOR 48
WDTCON — — — — — — —SWDTEN50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.