Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 311
PIC18F2585/2680/4585/4680
23.2.4 CAN BAUD RATE REGISTERS
This section describes the CAN Baud Rate registers.
REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1
Note: These registers are writable in
Configuration mode only.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0
bit 7-6 SJW1:SJW0: Synchronized Jump Width bits
11 = Synchronization jump width time = 4 x T
Q
10 = Synchronization jump width time = 3 x T
Q
01 = Synchronization jump width time = 2 x T
Q
00 = Synchronization jump width time = 1 x T
Q
bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/FOSC
111110 = T
Q = (2 x 63)/FOSC
:
:
000001 = TQ = (2 x 2)/FOSC
000000 = T
Q = (2 x 1)/FOSC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown