Datasheet

© 2007 Microchip Technology Inc. Preliminary DS39625C-page 255
PIC18F2585/2680/4585/4680
19.6 A/D Conversions
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 T
AD acquisition
time before the conversion starts.
Clearing the GO/DONE
bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 19-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 19-4: A/D CONVERSION T
AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2
TAD3
TAD4 TAD5
TAD6 TAD7
TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle:
1
2
3 4 5
6
7
8
11
Set GO bit
(Holding capacitor is disconnected)
9
10
Conversion starts
1
2
3 4
(Holding capacitor continues
acquiring input)
T
ACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0b9
b6
b5 b4
b3
b2
b1
b8
b7
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle: