Datasheet

PIC18F2585/2680/4585/4680
DS39625C-page 168 Preliminary © 2007 Microchip Technology Inc.
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN
(3)
— RI TO PD POR BOR 50
IPR1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR2
OSCFIP
CMIP
(2)
— EEIP BCLIP HLVDIP TMR3IP ECCP1IP
(2)
51
PIR2
OSCFIF
CMIF
(2)
— EEIF BCLIF HLVDIF TMR3IF ECCP1IF
(2)
52
PIE2
OSCFIE
CMIE
(2)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(2)
51
TRISB PORTB Data Direction Register 52
TRISC PORTC Data Direction Register 52
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 50
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 50
TMR3H Timer3 Register High Byte 51
TMR3L Timer3 Register Low Byte 51
T3CON RD16 T3ECCP1
(1)
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1 (LSB) 51
CCPR1H Capture/Compare/PWM Register 1 (MSB) 51
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
ECCPR1L
(1)
Enhanced Capture/Compare/PWM Register 1 (LSB) 51
ECCPR1H
(1)
Enhanced Capture/Compare/PWM Register 1 (MSB) 51
ECCP1CON
(1)
EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: These bits or registers are available on PIC18F4X8X devices only.
2: These bits are available on PIC18F4X8X devices and reserved on PIC18F2X8X devices.
3: The SBOREN bit is only available when CONFIG2L<1:0> =
01; otherwise, it is disabled and reads as ‘0’.