Datasheet

© 2009 Microchip Technology Inc. DS39637D-page 91
PIC18F2480/2580/4480/4580
B2D4
(8)
B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 63, 305
B2D3
(8)
B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 63, 305
B2D2
(8)
B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 63, 305
B2D1
(8)
B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D11 B2D10 xxxx xxxx 64, 305
B2D0
(8)
B2D07 B2D06 B2D05 B2D04 B2D03 B2D02 B2D01 B2D00 xxxx xxxx 64, 305
B2DLC
(8)
Receive mode
— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 64, 307
B2DLC
(8)
Transmit mode
—TXRTR— — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 64, 307
B2EIDL
(8)
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 64, 305
B2EIDH
(8)
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 64, 304
B2SIDL
(8)
Receive mode
SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 64, 303
B2SIDL
(8)
Transmit mode
SID2 SID1 SID0 —EXIDE —EID17EID16xxx- x-xx 64, 303
B2SIDH
(8)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 64, 302
B2CON
(8)
Receive mode
RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 64, 301
B2CON
(8)
Transmit mode
TXBIF RXM1 TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 64, 301
B1D7
(8)
B1D77 B1D76 B1D75 B1D74 B1D73 B1D72 B1D71 B1D70 xxxx xxxx 64, 305
B1D6
(8)
B1D67 B1D66 B1D65 B1D64 B1D63 B1D62 B1D61 B1D60 xxxx xxxx 64, 305
B1D5
(8)
B1D57 B1D56 B1D55 B1D54 B1D53 B1D52 B1D51 B1D50 xxxx xxxx 64, 305
B1D4
(8)
B1D47 B1D46 B1D45 B1D44 B1D43 B1D42 B1D41 B1D40 xxxx xxxx 64, 305
B1D3
(8)
B1D37 B1D36 B1D35 B1D34 B1D33 B1D32 B1D31 B1D30 xxxx xxxx 64, 305
B1D2
(8)
B1D27 B1D26 B1D25 B1D24 B1D23 B1D22 B1D21 B1D20 xxxx xxxx 64, 305
B1D1
(8)
B1D17 B1D16 B1D15 B1D14 B1D13 B1D12 B1D11 B1D10 xxxx xxxx 64, 305
B1D0
(8)
B1D07 B1D06 B1D05 B1D04 B1D03 B1D02 B1D01 B1D00 xxxx xxxx 64, 305
B1DLC
(8)
Receive mode
— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 64, 307
B1DLC
(8)
Transmit mode
—TXRTR— — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 64, 307
B1EIDL
(8)
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 64, 305
B1EIDH
(8)
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 64, 304
B1SIDL
(8)
Receive mode
SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 64, 303
B1SIDL
(8)
Transmit mode
SID2 SID1 SID0 —EXIDE —EID17EID16xxx- x-xx 64, 303
B1SIDH
(8)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 64, 302
B1CON
(8)
Receive mode
RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 64, 301
B1CON
(8)
Transmit mode
TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 64, 301
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.