Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 40 8-Bit 40 MHz I/O number 36

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Table Of Contents

Power-Managed Modes:
Flexible Oscillator Structure:
Special Microcontroller Features:
Peripheral Highlights:
ECAN Technology Module Features:
Pin Diagrams
Pin Diagrams (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 New Core Features
  - 1.1.1 nanoWatt Technology
  - 1.1.2 Multiple Oscillator Options and Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Guidelines for Getting Started with PIC18F Microcontrollers
- 2.1 Basic Connection Requirements
  - FIGURE 2-1: Recommended Minimum connections
- 2.2 Power Supply Pins
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 ICSP Pins
- 2.5 External Oscillator Pins
- 2.6 Unused I/Os
  - FIGURE 2-3: Suggested Placement of the Oscillator Circuit
3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Crystal Oscillator/Ceramic Resonators
- 3.3 External Clock Input
  - FIGURE 3-3: External Clock Input Operation (EC Configuration)
  - FIGURE 3-4: External Clock Input Operation (ECIO Configuration)
- 3.4 RC Oscillator
  - FIGURE 3-5: RC Oscillator Mode
  - FIGURE 3-6: RCIO Oscillator Mode
- 3.5 PLL Frequency Multiplier
  - 3.5.1 HSPLL Oscillator Mode
    - FIGURE 3-7: PLL Block Diagram (HS Mode)
  - 3.5.2 PLL and INTOSC
- 3.6 Internal Oscillator Block
- 3.7 Clock Sources and Oscillator Switching
- 3.8 Effects of Power-Managed Modes on the Various Clock Sources
- 3.9 Power-up Delays
  - TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode
4.0 Power-Managed Modes
- 4.1 Selecting Power-Managed Modes
- 4.2 Run Modes
- 4.3 Sleep Mode
- 4.4 Idle Modes
- 4.5 Exiting Idle and Sleep Modes
5.0 Reset
- 5.1 RCON Register
  - FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 5-1: RCON: Reset Control Register
- 5.2 Master Clear Reset (MCLR)
- 5.3 Power-on Reset (POR)
  - FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 5.4 Brown-out Reset (BOR)
- 5.5 Device Reset Timers
- 5.6 Reset State of Registers
  - TABLE 5-3: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 5-4: Initialization Conditions for All Registers
6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: Table Read Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads From Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing a Flash Program Memory Row
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 Data EEPROM Memory
- 8.1 EEADR Register
- 8.2 EECON1 and EECON2 Registers
  - Register 8-1: EECON1: Data EEPROM Control Register 1
- 8.3 Reading the Data EEPROM Memory
- 8.4 Writing to the Data EEPROM Memory
- 8.5 Write Verify
  - EXAMPLE 8-1: Data EEPROM Read
  - EXAMPLE 8-2: Data EEPROM Write
- 8.6 Operation During Code-Protect
- 8.7 Protection Against Spurious Write
- 8.8 Using the Data EEPROM
  - EXAMPLE 8-3: Data EEPROM Refresh Routine
  - TABLE 8-1: Registers Associated with Data EEPROM Memory
9.0 8 x 8 Hardware Multiplier
- 9.1 Introduction
- 9.2 Operation
10.0 Interrupts
- FIGURE 10-1: Interrupt Logic
- 10.1 INTCON Registers
- 10.2 PIR Registers
- 10.3 PIE Registers
- 10.4 IPR Registers
- 10.5 RCON Register
  - Register 10-13: RCON: Reset Control Register
- 10.6 INTx Pin Interrupts
- 10.7 TMR0 Interrupt
- 10.8 PORTB Interrupt-on-Change
- 10.9 Context Saving During Interrupts
  - EXAMPLE 10-1: Saving STATUS, Wreg and Bsr Registers in RAM
11.0 I/O Ports
- FIGURE 11-1: Generic I/O Port Operation
- 11.1 PORTA, TRISA and LATA Registers
- 11.2 PORTB, TRISB and LATB Registers
- 11.3 PORTC, TRISC and LATC Registers
- 11.4 PORTD, TRISD and LATD Registers
- 11.5 PORTE, TRISE and LATE Registers
  - EXAMPLE 11-5: Initializing PORTE
  - 11.5.1 PORTE in 28-Pin Devices
- 11.6 Parallel Slave Port
12.0 Timer0 Module
- Register 12-1: T0CON: Timer0 Control Register
- 12.1 Timer0 Operation
- 12.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)
- 12.3 Prescaler
  - 12.3.1 Switching Prescaler Assignment
- 12.4 Timer0 Interrupt
  - TABLE 12-1: Registers Associated with Timer0
13.0 Timer1 Module
- Register 13-1: T1CON: Timer1 Control Register
- 13.1 Timer1 Operation
  - FIGURE 13-1: Timer1 Block Diagram
  - FIGURE 13-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 13.2 Timer1 16-Bit Read/Write Mode
- 13.3 Timer1 Oscillator
- 13.4 Timer1 Interrupt
- 13.5 Resetting Timer1 Using the CCP Special Event Trigger
- 13.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter
14.0 Timer2 Module
- 14.1 Timer2 Operation
  - Register 14-1: T2CON: Timer2 Control Register
- 14.2 Timer2 Interrupt
- 14.3 TMR2 Output
  - FIGURE 14-1: Timer2 Block Diagram
  - TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter
15.0 Timer3 Module
- Register 15-1: T3CON: Timer3 Control Register
- 15.1 Timer3 Operation
  - FIGURE 15-1: Timer3 Block Diagram
  - FIGURE 15-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 15.2 Timer3 16-Bit Read/Write Mode
- 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 15.4 Timer3 Interrupt
- 15.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 15-1: Registers Associated with Timer3 as a Timer/Counter
16.0 Capture/Compare/PWM (CCP) Modules
- Register 16-1: CCP1CON: Capture/Compare/PWM Control Register
- 16.1 CCP Module Configuration
  - 16.1.1 CCP Modules and Timer Resources
    - TABLE 16-1: CCP Mode – Timer Resource
    - TABLE 16-2: Interactions Between CCP1 and ECCP1 for Timer Resources
- 16.2 Capture Mode
- 16.3 Compare Mode
- 16.4 PWM Mode
17.0 Enhanced Capture/Compare/PWM (ECCP) Module
- Register 17-1: ECCP1CON Register (ECCP1 module, PIC18F4480/4580 Devices)
- 17.1 ECCP Outputs and Configuration
  - 17.1.1 ECCP Modules and Timer Resources
- 17.2 Capture and Compare Modes
  - 17.2.1 Special Event Trigger
- 17.3 Standard PWM Mode
  - TABLE 17-1: Pin Assignments for Various ECCP Modes
- 17.4 Enhanced PWM Mode
18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- 18.4 I2C Mode
19.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)
- Register 19-1: TXSTA: Transmit Status And Control Register
- Register 19-2: RCSTA: Receive Status And Control Register
- Register 19-3: BAUDCON: Baud Rate Control Register
- 19.1 Baud Rate Generator (BRG)
- 19.2 EUSART Asynchronous Mode
- 19.3 EUSART Synchronous Master Mode
  - 19.3.1 EUSART Synchronous Master Transmission
  - 19.3.2 EUSART Synchronous Master Reception
    - FIGURE 19-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 19-8: Registers Associated with Synchronous Master Reception
- 19.4 EUSART Synchronous Slave Mode
  - 19.4.1 EUSART Synchronous Slave Transmit
    - TABLE 19-9: Registers Associated with Synchronous Slave Transmission
  - 19.4.2 EUSART Synchronous Slave Reception
    - TABLE 19-10: Registers Associated with Synchronous Slave Reception
20.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- Register 20-3: ADCON2: A/D Control Register 2
- FIGURE 20-1: A/D Block Diagram
- FIGURE 20-2: Analog Input Model
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting and Configuring Automatic Acquisition Time
- 20.3 Selecting the A/D Conversion Clock
  - TABLE 20-1: Tad vs. Device Operating Frequencies
- 20.4 Operation in Power-Managed Modes
- 20.5 Configuring Analog Port Pins
- 20.6 A/D Conversions
  - FIGURE 20-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 20-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 20.7 Use of the CCP1 Trigger
  - TABLE 20-2: Registers Associated with A/D Operation
21.0 Comparator Module
- Register 21-1: CMCON: Comparator Control Register
- 21.1 Comparator Configuration
  - FIGURE 21-1: Comparator I/O Operating Modes
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
  - FIGURE 21-3: Comparator Output Block Diagram
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
  - FIGURE 21-4: Comparator Analog Input Model
  - TABLE 21-1: Registers Associated With Comparator Module
22.0 Comparator Voltage Reference Module
- 22.1 Configuring the Comparator Voltage Reference
  - Register 22-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 22-1: Comparator Voltage Reference Block Diagram
- 22.2 Voltage Reference Accuracy/Error
- 22.3 Operation During Sleep
- 22.4 Effects of a Reset
- 22.5 Connection Considerations
  - FIGURE 22-2: Comparator Voltage Reference Output Buffer Example
  - TABLE 22-1: Registers Associated with Comparator Voltage Reference
23.0 High/Low-Voltage Detect (HLVD)
- Register 23-1: HLVDCON: High/Low-Voltage Detect Control Register
- 23.1 Operation
  - FIGURE 23-1: HLVD MOdule Block Diagram (with External Input)
- 23.2 HLVD Setup
- 23.3 Current Consumption
- 23.4 HLVD Start-up Time
  - FIGURE 23-2: Low-Voltage Detect Operation (VDIRMAG = 0)
  - FIGURE 23-3: High-Voltage Detect Operation (VDIRMAG = 1)
- 23.5 Applications
  - FIGURE 23-4: Typical Low-Voltage Detect Application
- 23.6 Operation During Sleep
- 23.7 Effects of a Reset
  - TABLE 23-1: Registers Associated with High/Low-Voltage Detect Module
24.0 ECAN Module
- 24.1 Module Overview
  - 24.1.1 Module Functionality
    - FIGURE 24-1: CAN Buffers and Protocol Engine Block Diagram
- 24.2 CAN Module Registers
- 24.3 CAN Modes of Operation
- 24.4 CAN Module Functional Modes
- 24.5 CAN Message Buffers
- 24.6 CAN Message Transmission
- 24.7 Message Reception
- 24.8 Message Acceptance Filters and Masks
  - TABLE 24-2: Filter/Mask Truth Table
  - FIGURE 24-3: Message Acceptance Mask and Filter Operation
- 24.9 Baud Rate Setting
- 24.10 Synchronization
- 24.11 Programming Time Segments
- 24.12 Oscillator Tolerance
- 24.13 Bit Timing Configuration Registers
- 24.14 Error Detection
- 24.15 CAN Interrupts
25.0 Special Features of the CPU
- 25.1 Configuration Bits
- 25.2 Watchdog Timer (WDT)
  - 25.2.1 Control Register
- 25.3 Two-Speed Start-up
  - 25.3.1 Special Considerations for Using Two-Speed Start-up
    - FIGURE 25-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
- 25.4 Fail-Safe Clock Monitor
- 25.5 Program Verification and Code Protection
- 25.6 ID Locations
- 25.7 In-Circuit Serial Programming
- 25.8 In-Circuit Debugger
  - TABLE 25-4: Debugger Resources
- 25.9 Single-Supply ICSP Programming
26.0 Instruction Set Summary
- 26.1 Standard Instruction Set
- 26.2 Extended Instruction Set
27.0 Development Support
- 27.1 MPLAB Integrated Development Environment Software
- 27.2 MPLAB C Compilers for Various Device Families
- 27.3 HI-TECH C for Various Device Families
- 27.4 MPASM Assembler
- 27.5 MPLINK Object Linker/ MPLIB Object Librarian
- 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.7 MPLAB SIM Software Simulator
- 27.8 MPLAB REAL ICE In-Circuit Emulator System
- 27.9 MPLAB ICD 3 In-Circuit Debugger System
- 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 27.12 MPLAB PM3 Device Programmer
- 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
28.0 Electrical Characteristics
- Absolute Maximum Ratings (†)
  - FIGURE 28-1: PIC18F2480/2580/4480/4580 Voltage-Frequency Graph (Industrial, Extended)
  - FIGURE 28-2: PIC18LF2480/2580/4480/4580 Voltage-Frequency Graph (Industrial)
- 28.1 DC Characteristics: Supply Voltage PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial)
- 28.2 DC Characteristics: Power-Down and Supply Current PIC18F2480/2580/4480/4580 (Industrial, Extended) PIC18LF2480/2580/4480/4580 (Industrial)
- 28.3 DC Characteristics: PIC18F2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 (Industrial)
- 28.4 AC (Timing) Characteristics
29.0 Packaging Information
- 29.1 Package Marking Information
- 29.1 Package Marking Information (Continued)
- 29.2 Package Details
Appendix A: Revision History
- Revision A (July 2004)
- Revision B (August 2006)
- Revision C (March 2007)
- Revision D (November 2009)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Conversion Considerations
Appendix D: Migration from Baseline to Enhanced Devices
Appendix E: Migration From Mid-Range to Enhanced Devices
Appendix F: Migration From High-End to Enhanced Devices
INDEX
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PIC18F2480/2580/4480/4580

TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page:

PORTA RA7

(1)

RA6

(1)

RA5 RA4 RA3 RA2 RA1 RA0 58

LATA LATA7

(1)

LATA6

(1)

LATA Output Latch Register 58

TRISA TRISA7

(1)

TRISA6

(1)

PORTA Data Direction Register 58

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56

CVRCON

(2)

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

2: These registers are unimplemented on PIC18F2X80 devices.