Datasheet

© 2009 Microchip Technology Inc. DS39637D-page 457
PIC18F2480/2580/4480/4580
FIGURE 28-22: A/D CONVERSION TIMING
TABLE 28-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period PIC18FXXXX 0.7 25.0
(1)
μsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0
(1)
μsVDD = 2.0V;
T
OSC based, VREF full range
PIC18FXXXX — 1 μs A/D RC mode
PIC18LFXXXX — 3 μsV
DD = 2.0V;
A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time) (Note 2)
11 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4 — μs-40°C to +85°C
135 T
SWC Switching Time from Convert → Sample — (Note 4) —
136 TAMP Amplifier Settling Time (Note 5) 1—μs This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on C
HOLD).
Note 1: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.
2: ADRES register may be read on the following T
CY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
DD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the following cycle of the device clock.
5: See Section 20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY