Datasheet

© 2009 Microchip Technology Inc. DS39637D-page 37
PIC18F2480/2580/4480/4580
3.8 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the
power-managed mode (see Section 25.2 “Watchdog
Timer (WDT)”, Section 25.3 “Two-Speed Start-up”
and Section 25.4 “Fail-Safe Clock Monitor” for more
information on WDT, Two-Speed Start-up and Fail-Safe
Clock Monitor. The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
The INTOSC output is enabled for Two-Speed Start-up
at 1 MHz after a Reset.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock (RTC). Other features may be operat-
ing that do not require a device clock source (i.e.,
MSSP slave, PSP, INTx pins and others). Peripherals
that may add significant current consumption are listed
in Section 28.2 “DC Characteristics: Power Down
and Supply Current”.
3.9 Power-up Delays
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 5.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-10). It is enabled by clearing (= 0) the
PWRTEN
Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval, T
CSD (parameter 38,
Table 28-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note: See Table 5-2 in Section 5.0 “Reset”, for time-outs due to Sleep and MCLR
Reset.