PIC18F2480/2580/4480/4580 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F2480/2580/4480/4580 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Peripheral Highlights: • • • • • • • • • • • • Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Idle mode Currents Down to 6.1 μA Typical Sleep mode Current Down to 0.2 μA Typical Timer1 Oscillator: 1 μA, 32 kHz, 2V Watchdog Timer: 1.
PIC18F2480/2580/4480/4580 Pin Diagrams MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 28-Pin QFN 28 27 26 25 24 23 22 21 20 1
PIC18F2480/2580/4480/4580 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 PIC18F4480 PIC18F4580 NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI NC NC RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CA
PIC18F2480/2580/4480/4580 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 25 3.0 Oscillator Configurations ............................................................................
PIC18F2480/2580/4480/4580 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 8 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • • • • PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory.
PIC18F2480/2580/4480/4580 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control.
PIC18F2480/2580/4480/4580 TABLE 1-1: DEVICE FEATURES Features PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 20 20 Interrupt Sources 19 19 Ports A, B, C, (E) Ports A, B, C, (E) Timers 4 4 4 4 Capture/Compare/PWM Modules 1
PIC18F2480/2580/4480/4580 FIGURE 1-1: PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch Program Memory (16/32 Kbytes) STKPTR Data Latch 8 Instruction Bus <16> RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Memory (.7, 1.
PIC18F2480/2580/4480/4580 FIGURE 1-2: PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Memory (.7, 1.
PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS Pin Number Pin SPDIP, QFN Type SOIC Pin Name MCLR/VPP/RE3 MCLR 1 26 VPP RE3 OSC1/CLKI/RA7 OSC1 9 I ST P I ST 6 I I CLKI I/O RA7 OSC2/CLKO/RA6 OSC2 10 Buffer Type Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin SPDIP, QFN Type SOIC Pin Name Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/ HLVDIN RA5 AN4 SS HLVDIN 7 27 I/O I TTL Analog Digital I/O. Analog Input 0. I/O I TTL Analog Digital I/O. Analog Input 1. I/O I I TTL Analog Analog Digital I/O.
PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin SPDIP, QFN Type SOIC Pin Name Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin SPDIP, QFN Type SOIC Pin Name Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI RC1 T1OSI 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 RE3 — — VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP QFN 1 18 Pin Buffer TQFP Type Type 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 32 ST P I ST 30 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 CLKO RA6 Legend: TTL ST O I2C I 14 33 Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RA0/AN0/CVREF RA0 AN0 CVREF 2 19 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/ HLVDIN RA5 AN4 SS HLVDIN 7 Pin Buffer TQFP Type Type Description PORTA is a bidirectional I/O port. 20 21 22 23 24 19 I/O I O TTL Analog Analog Digital I/O. Analog Input 0. Analog comparator reference output.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 34 RC1/T1OSI RC1 T1OSI 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 Pin Buffer TQFP Type Type Description PORTC is a bidirectional I/O port. 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 Legend: TTL ST O I2C 42 43 44 1 ST — ST I/O I ST CMOS I/O I/O ST ST Digital I/O.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.
PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP QFN Pin Buffer TQFP Type Type Description PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD 8 25 25 AN5 RE1/WR/AN6/C1OUT RE1 WR 9 26 10 27 ST TTL I Analog I/O I ST TTL I O Analog TTL I/O I ST TTL I O Analog TTL Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog Input 5. 26 AN6 C1OUT RE2/CS/AN7/C2OUT RE2 CS I/O I Digital I/O.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 24 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.
PIC18F2480/2580/4480/4580 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F2480/2580/4480/4580 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1.
PIC18F2480/2580/4480/4580 2.5 External Oscillator Pins FIGURE 2-3: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F2480/2580/4480/4580 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types PIC18F2480/2580/4480/4580 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL Enabled 5. RC External Resistor/Capacitor with FOSC/4 Output on RA6 6.
PIC18F2480/2580/4480/4580 TABLE 3-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-2. FIGURE 3-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 Clock from Ext.
PIC18F2480/2580/4480/4580 3.4 RC Oscillator 3.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (REXT) and capacitor (CEXT) • operating temperature Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations.
PIC18F2480/2580/4480/4580 3.6 Internal Oscillator Block The PIC18F2480/2580/4480/4580 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock.
PIC18F2480/2580/4480/4580 REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F2480/2580/4480/4580 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2480/2580/4480/4580 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2480/2580/4480/4580 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
PIC18F2480/2580/4480/4580 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<3:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
PIC18F2480/2580/4480/4580 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Intern
PIC18F2480/2580/4480/4580 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 38 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 4.0 POWER-MANAGED MODES 4.1.1 The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F2480/2580/4480/4580 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18F2480/2580/4480/4580 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
PIC18F2480/2580/4480/4580 On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see FIGURE 4-1: Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock.
PIC18F2480/2580/4480/4580 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4).
PIC18F2480/2580/4480/4580 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F2480/2580/4480/4580 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared.
PIC18F2480/2580/4480/4580 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator.
PIC18F2480/2580/4480/4580 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F2480/2580/4480/4580 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT, HS or HSPLL modes.
PIC18F2480/2580/4480/4580 5.0 RESET The PIC18F2480/2580/4480/4580 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers.
PIC18F2480/2580/4480/4580 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN:
PIC18F2480/2580/4480/4580 5.2 Master Clear Reset (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 5-2: In PIC18F2480/2580/4480/4580 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.
PIC18F2480/2580/4480/4580 5.4 Brown-out Reset (BOR) PIC18F2480/2580/4480/4580 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV<1:0> bits.
PIC18F2480/2580/4480/4580 5.5 Device Reset Timers 5.5.3 PIC18F2480/2580/4480/4580 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.
PIC18F2480/2580/4480/4580 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39637D-page 52 ©
PIC18F2480/2580/4480/4580 FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) FIGURE 5-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on a Power-on Reset and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation.
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets TOSU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2480 2580 4480 4580 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---u uuuu PCLA
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BSR 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu INDF2 2480 2580 4480 4580 N/A N/A N/A Register POSTINC2 2480 2580 4480 4580 N/A N/A N/A POSTDEC2 2480 2580 4480 4580 N/A N/A N/A PREINC2 2480 2580 4480 4580 N/A N/A N/A PLUSW2 2480 2580 4480 4580
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ADCON2 2480 2580 4480 4580 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu ECCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uu
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu(1) 2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu-(1) Register PIR2 PIE2 IPR1 PIR1 PIE1 Wake-up via WDT or Interrupt 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu 2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu- 2480 2580 4480 4580
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BRGCON3 2480 2580 4480 4580 00-- -000 00-- -000 uu-- -uuu BRGCON2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu Register BRGCON1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu CANCON 2480 2580 4480 4580 1000 000- 1000 000- uuuu uuu- CANSTAT 2480 258
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXB1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 2480 2580 4480 4580 000- 0000 000- 0000 uuu- uuuu TXB0D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 2480 2580 4480 4580
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TXB2D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 2480 2580 4480 4580 x
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF3SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 2480 2580 44
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B4D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B4D0(6) 2480 2580 4480 4580
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B2D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu (6) B2DLC 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B2EIDH(6) 2480 2580
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B0EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu B0CON(6) 2480 2580 4480
PIC18F2480/2580/4480/4580 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF13EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu Register Applicable Devices (6) RXF13SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuu
PIC18F2480/2580/4480/4580 6.0 MEMORY ORGANIZATION 6.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
PIC18F2480/2580/4480/4580 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F2480/2580/4480/4580 6.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits.
PIC18F2480/2580/4480/4580 6.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset.
PIC18F2480/2580/4480/4580 6.2 PIC18 Instruction Cycle 6.2.1 6.2.2 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F2480/2580/4480/4580 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 6.1.1 “Program Counter”).
PIC18F2480/2580/4480/4580 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory.
PIC18F2480/2580/4480/4580 FIGURE 6-5: DATA MEMORY MAP FOR PIC18F2480/4480 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 DS39637D-page 74 When a = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 000h 05Fh 060h 0FFh 100h 1FFh 200h FFh 00h GPR FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh
PIC18F2480/2580/4480/4580 FIGURE 6-6: DATA MEMORY MAP FOR PIC18F2580/4580 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When a = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 000h 05Fh 060h 0FFh 100h 1FFh 200h FFh 00h GPR FFh 00h 2FFh 300h GPR FFh 00h 7FFh 800h FFh 00h 8FFh 900h FFh 00h AFFh B00h FFh 00h BFFh C00h FFh Bank 13 00h CFFh D00h Ban
PIC18F2480/2580/4480/4580 FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 Bank Select(2) 0 0 1 1 000h Data Memory 00h Bank 0 FFh 00h 100h Bank 1 1 1 1 1 1 1 0 1 1 FFh 00h 200h 300h From Opcode(2) 7 Bank 2 FFh 00h Bank 3 through Bank 13 FFh 00h E00h Bank 14 FFh 00h F00h FFFh Note 1: 2: 6.3.
PIC18F2480/2580/4480/4580 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 6-1 and Table 6-2.
PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address Name Address Name Address Name F7Fh — F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F7Eh — F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH
PIC18F2480/2580/4480/4580 TABLE 6-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Name EFFh — Address Name EDFh — Address Name EBFh — Address Name E9Fh — EFEh — EDEh — EBEh — E9Eh — EFDh — EDDh — EBDh — E9Dh — EFCh — EDCh — EBCh — E9Ch — EFBh — EDBh — EBBh — E9Bh — EFAh — EDAh — EBAh — E9Ah — EF9h — ED9h — EB9h — E99h — EF8h — ED8h — EB8h — E98h — EF7h — ED7h — EB7h — E97h — EF6h — ED
PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address E7Fh CANCON_RO4 E7Eh CANSTAT_RO4 E7Dh B5D7(2) E6Fh Name CANCON_RO5 E6Eh CANSTAT_RO5 Address CANCON_RO6 E4Fh Name CANCON_RO7 E5Eh CANSTAT_RO6 B3D7(2) E4Dh B2D7(2) E6Ch B4D6 (2) E5Ch B3D6 (2) E4Ch B2D6(2) E6Bh B4D5(2) E5Bh B3D5(2) E4Bh B2D5(2) E6Ah B4D4(2) E5Ah B3D4(2) E4Ah B2D4(2) E69h B4D3 (2) E59h B3D3 (2) E49h B2D3(2) E6
PIC18F2480/2580/4480/4580 TABLE 6-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Name DFFh — Address Name DDFh — Address Name DBFh — Address Name D9Fh — DFEh — DDEh — DBEh — D9Eh — DFDh — DDDh — DBDh — D9Dh — DFCh TXBIE DDCh — DBCh — D9Ch — DFBh — DDBh — DBBh — D9Bh — DFAh BIE0 DDAh — DBAh — D9Ah — DF9h — DD9h — DB9h — D99h — DF8h BSEL0 DD8h SDFLC DB8h — D98h — DF7h — DD7h — DB7h — D97h
PIC18F2480/2580/4480/4580 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name D7Fh — D7Eh — D7Dh — D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh — D6Eh — D6Dh — D6Ch — D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name TOSU REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) Bit 7 Bit 6 Bit 5 — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — bit 21(1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on Details on POR, BOR Page: ---0 0000 55, 68 0000 0000 55, 68 0000 0000 55, 68 Return Stack Pointer 00-0 0000 55, 69 Holding Register for PC<20:16> ---0 00
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name FSR2H FSR2L REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 — — — — Bit 3 Bit 2 Bit 1 Bit 0 Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte — STATUS — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte — N OV Z DC C Value on Details on POR, BOR Page: ---- xxxx 56, 96 xxxx xxxx 56, 96 ---x xxxx 56, 94 0000 0000 56, 153 xxxx xxxx 56, 1
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on Details on POR, BOR Page: Bit 0 SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 57, 236 SPBRG EUSART Baud Rate Generator 0000 0000 57, 236 RCREG EUSART Receive Register 0000 0000 57, 244 TXREG EUSART Transmit Register 0000 0000 57, 241 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 243 RCSTA SP
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name PORTE(3) REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — — RE3(5) RE2(3) RE1(3) RE0(3) Value on Details on POR, BOR Page: ---- xxxx 58, 150 PORTD(3) PORTD Data Direction Register xxxx xxxx 58, 143 PORTC PORTC Data Direction Register xxxx xxxx 58, 141 PORTB PORTB Data Direction Register xxxx xxxx 58, 138 xx00 0000 58, 135 RA7(6) RA6(6) ECANCON MDSEL1 MDSEL0
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RXB0CON Mode 0 RXFUL RXM1 RXM0(7) —(7) RXB0CON Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D4 RXB1D47 RXB1D46 RXB1D3 RXB1D37 RXB1D2 Bit 2 Value on Details on POR, BOR Page: Bit 1 Bit 0 JTOFF(7) FILHIT0(7) 000- 0000 59
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details on POR, BOR Page: TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 60, 290 — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 60, 291 60, 290 TXB1DLC 60, 290 TXB1EIDL EID7 EID6 EID5 EID4
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 RXF2SIDL SID2 SID1 SID0 — EXIDEN — RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 RXF1SIDL SID2 SID1 SID0
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on POR, BOR Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B4D2(8) B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 xxxx xxxx 63, 305 B4D1(8) B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 xxxx xxxx 63, 305 B4D0(8) B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 xxxx xxxx 62, 305 B4DLC(8) Receive mode — RXRTR RB1 RB0 DLC3 DLC2
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on POR, BOR Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B2D4(8) B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 63, 305 B2D3(8) B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 63, 305 B2D2(8) B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 63, 305 B2D1(8) B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D1
PIC18F2480/2580/4480/4580 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Value on Details on POR, BOR Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0D7(8) B0D77 B0D76 B0D75 B0D74 B0D73 B0D72 B0D71 B0D70 xxxx xxxx 64, 305 B0D6(8) B0D67 B0D66 B0D65 B0D64 B0D63 B0D62 B0D61 B0D60 xxxx xxxx 64, 305 B0D5(8) B0D57 B0D56 B0D55 B0D54 B0D53 B0D52 B0D51 B0D50 xxxx xxxx 64, 305 B0D4(8) B0D47 B0D46 B0D45 B0D44 B0D43 B0D42 B0D4
PIC18F2480/2580/4480/4580 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) Bit 0 Value on Details on POR, BOR Page: EID9 EID8 xxxx xxxx 65, 309 EID17 EID16 xxx- x-xx 65, 308 SID4 SID3 xxxx xxxx 65, 309 EID2 EID1 EID0 xxxx xxxx 65, 309 EID11 EID10 EID9 EID8 xxxx xxxx 65, 309 — EXIDEN — EID17 EID16 xxx- x-xx 65, 308 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 65, 309 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 66, 309 EID14 EID13 EID12 EID11
PIC18F2480/2580/4480/4580 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
PIC18F2480/2580/4480/4580 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F2480/2580/4480/4580 6.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F2480/2580/4480/4580 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F2480/2580/4480/4580 6.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. 6.
PIC18F2480/2580/4480/4580 FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as the SFRs, or locations F60h to 0FFh (Bank 15) of data memory.
PIC18F2480/2580/4480/4580 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower half of Access RAM (00h to 7Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F2480/2580/4480/4580 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable, during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time.
PIC18F2480/2580/4480/4580 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
PIC18F2480/2580/4480/4580 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Fl
PIC18F2480/2580/4480/4580 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F2480/2580/4480/4580 7.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words.
PIC18F2480/2580/4480/4580 7.4 Erasing Flash Program Memory 7.4.1 The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F2480/2580/4480/4580 7.5 Writing to Flash Program Memory The minimum programming block is 16 words or 32 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory.
PIC18F2480/2580/4480/4580 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ;
PIC18F2480/2580/4480/4580 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DECFSZ BRA BSF BCF Required Sequence 7.5.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 110 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18F2480/2580/4480/4580 REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Fl
PIC18F2480/2580/4480/4580 8.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
PIC18F2480/2580/4480/4580 8.6 Operation During Code-Protect 8.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 25.0 “Special Features of the CPU” for additional information. 8.
PIC18F2480/2580/4480/4580 TABLE 8-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 INTCON GIE/GIEH PEIE/GIEL EEADR EEPROM Address Register 57 EEDATA EEPROM Data Register 57 EECON2 EEPROM Control Register 2 (not a physical register) EECON1 — FREE WRERR 57 WREN EEPGD CFGS IPR2 OSCFIP CMIP(1) — EEIP BCLIP HLVDIP PIR2 OSCFIF CMIF(1) — EEIF BCLIF HLVDIF O
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 116 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F2480/2580/4480/4580 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F2480/2580/4480/4580 10.0 INTERRUPTS The PIC18F2480/2580/4480/4580 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The highpriority interrupt vector is at 000008h and the lowpriority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F2480/2580/4480/4580 FIGURE 10-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Sleep Mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIEH/GIE TMR1IF TMR1IE TMR1IP IPE IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral I
PIC18F2480/2580/4480/4580 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F2480/2580/4480/4580 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt
PIC18F2480/2580/4480/4580 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priori
PIC18F2480/2580/4480/4580 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 10-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, GIE (INTCON<7>).
PIC18F2480/2580/4480/4580 REGISTER 10-5: R/W-0 PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 (1) OSCFIF CMIF U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleare
PIC18F2480/2580/4480/4580 REGISTER 10-6: Mode 0 Mode 1,2 R/W-0 PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXBnIF (1) TXB1IF R/W-0 TXB0IF (1) R/W-0 TXB0IF (1) R/W-0 R/W-0 RXB1IF RXB0IF R/W-0 R/W-0 RXBnIF FIFOWMIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
PIC18F2480/2580/4480/4580 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F2480/2580/4480/4580 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE(1) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit
PIC18F2480/2580/4480/4580 REGISTER 10-9: Mode 0 Mode 1,2 PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x =
PIC18F2480/2580/4480/4580 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F2480/2580/4480/4580 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 (1) OSCFIP CMIP U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High prior
PIC18F2480/2580/4480/4580 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 Mode 0 Mode 1,2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP (1) TXBnIP TXB1IP R/W-1 (1) TXB0IP R/W-1 (1) TXB0IP R/W-1 R/W-1 RXB1IP RXB0IP R/W-1 R/W-1 RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC18F2480/2580/4480/4580 10.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities.
PIC18F2480/2580/4480/4580 10.6 INTx Pin Interrupts 10.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18F2480/2580/4480/4580 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F2480/2580/4480/4580 TABLE 11-1: PORTA I/O SUMMARY Pin Name RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Legend: Note 1: Function I/O TRIS Buffer Description RA0 OUT 0 DIG LATA<0> data output. IN 1 TTL PORTA<0> data input. AN0 IN 1 ANA A/D Input Channel 0. Enabled on POR; this analog input overrides the digital input (read as clear – low level). CVREF(1) OUT x ANA Comparator voltage reference analog output.
PIC18F2480/2580/4480/4580 TABLE 11-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 (1) LATA6(1) LATA Output Latch Register LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register ADCON1 CVRCON(2) Reset Values on Page: 58 58 58 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 56 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 57 Legend: — = unimplemented, read as ‘0’.
PIC18F2480/2580/4480/4580 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATB) is also memory mapped.
PIC18F2480/2580/4480/4580 TABLE 11-3: PORTB I/O SUMMARY Pin Name Function I/O RB0/INT0/FLT0/AN10 RB0 OUT 0 DIG LATB<0> data output. IN 1 TTL PORTB<0> data input. Weak pull-up available only in this mode. External Interrupt 0 input. RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: TRIS Buffer Description INT0 IN 1 ST FLT0(1) IN 1 ST AN10 IN 1 ANA A/D Input Channel 10.
PIC18F2480/2580/4480/4580 TABLE 11-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 58 LATB LATB Output Latch Register 58 TRISB PORTB Data Direction Register 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTEDG0 INTEDG1 INTEDG2 RBIE TMR0IF INT0IF RBIF 55 — TMR0IP — RBIP 55 INTCON2 RBPU INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 55 ADCON1 —
PIC18F2480/2580/4480/4580 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATC) is also memory mapped.
PIC18F2480/2580/4480/4580 TABLE 11-5: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC7/RX/DT PORTC I/O TRIS Buffer RC0 OUT 0 DIG LATC<0> data output. IN 1 ST PORTC<0> data input. T1OSO OUT x ANA T13CKI IN 1 ST Timer1/Timer3 clock input. RC1 OUT 0 DIG LATC<1> data output. IN 1 ST PORTC<1> data input. T1OSI IN x ANA Timer1 oscillator input – overrides the TRIS<1> control when enabled. RC2 OUT 0 DIG LATC<2> data output.
PIC18F2480/2580/4480/4580 11.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4X80 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F2480/2580/4480/4580 TABLE 11-7: Pin Name RD0/PSP0/ C1IN+ PORTD I/O SUMMARY Function I/O TRIS Buffer RD0 OUT 0 DIG LATD<0> data output. IN 1 ST PORTD<0> data input. OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). IN x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled). C1IN+ IN 1 ANA Comparator 1 Positive Input B. Default on POR.
PIC18F2480/2580/4480/4580 TABLE 11-8: Name PORTD(1) SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD(1) LATD Output Latch Register 58 TRISD(1) PORTD Data Direction Register 58 TRISE(1) IBF OBF ECCP1CON(1) EPWM1M1 EPWM1M0 Legend: Note 1: IBOV PSPMODE EDC1B1 EDC1B0 — TRISE2 TRISE1 TRISE0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 58 57 — = unimplemented, read as ‘0’.
PIC18F2480/2580/4480/4580 11.5 PORTE, TRISE and LATE Registers Depending on the particular PIC18F2480/2580/4480/ 4580 device selected, PORTE is implemented in two different ways. For PIC18F4X80 devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and RE2/CS/AN7/C2OUT) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE.
PIC18F2480/2580/4480/4580 REGISTER 11-1: TRISE REGISTER (PIC18F4X80 DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output
PIC18F2480/2580/4480/4580 TABLE 11-9: PORTE I/O SUMMARY Pin Name Function I/O RE0 OUT 0 DIG LATE<0> data output. IN 1 ST PORTE<0> data input. RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT MCLR/VPP/RE3 Legend: TRIS Buffer Description RD IN 1 TTL PSP read enable input. AN5 IN 1 ANA A/D Input Channel 5. Enabled on POR; this analog input overrides the digital input (read as clear – low level). RE1 OUT 0 DIG LATE<1> data output. IN 1 ST PORTE<1> data input.
PIC18F2480/2580/4480/4580 11.6 Note: Parallel Slave Port The Parallel Slave Port is only available on PIC18F4X80 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 11-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation, as long as the Enhanced CCP module is not operating in dual output or quad output PWM mode.
PIC18F2480/2580/4480/4580 FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 58 LATD (1) TRISD(1) (1)
PIC18F2480/2580/4480/4580 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software-selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F2480/2580/4480/4580 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”).
PIC18F2480/2580/4480/4580 12.3 Prescaler 12.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 154 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 13.
PIC18F2480/2580/4480/4580 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F2480/2580/4480/4580 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F2480/2580/4480/4580 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F2480/2580/4480/4580 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 160 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 14.0 TIMER2 MODULE 14.
PIC18F2480/2580/4480/4580 14.2 Timer2 Interrupt 14.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F2480/2580/4480/4580 15.0 TIMER3 MODULE The Timer3 module timer/counter incorporates these features: • Software-selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: R/W-0 RD16 A simplified block diagram of the Timer3 module is shown in Figure 15-1.
PIC18F2480/2580/4480/4580 15.1 Timer3 Operation cycle (Fosc/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled. Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F2480/2580/4480/4580 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 166 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2480/2580 devices have one CCP module. PIC18F4480/4580 devices have two CCP (Capture/Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Capture, Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP implementation is discussed in Section 17.0 “Enhanced Capture/Compare/PWM (ECCP) Module”.
PIC18F2480/2580/4480/4580 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1, 2 or 3, depending on the mode selected.
PIC18F2480/2580/4480/4580 16.2 Capture Mode In Capture mode, the CCPR1H:CCPR1L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP1 pin (RB3 or RC1, depending on device configuration). An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge The event is selected by the mode select bits, CCP1M<3:0> (CCP1CON<3:0>).
PIC18F2480/2580/4480/4580 FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF T3ECCP1 CCP1 pin Prescaler ÷ 1, 4, 16 and Edge Detect Q1:Q4 ECCP1CON<3:0> 4 4 CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L Set ECCP1IF 4 T3CCP1 T3ECCP1 ECCP1 pin Prescaler ÷ 1, 4, 16 TMR3L TMR3 Enable CCPR1H T3ECCP1 CCP1CON<3:0> TMR3H and Edge Detect TMR3 Enable ECCPR1H ECCPR1L TMR1 Enable T3ECCP1 T3CCP1 DS39637D-page 170 TMR1H TMR1L © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 16.3 Compare Mode 16.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP1 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 16.3.
PIC18F2480/2580/4480/4580 TABLE 16-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 RCON IPEN SBOREN(3) — RI TO PD POR BOR 56 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58
PIC18F2480/2580/4480/4580 16.4 PWM Mode FIGURE 16-4: Period In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with a PORTB or PORTC data latch, the appropriate TRIS bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the RC2 output latch (depending on device configuration) to the default low level. This is not the PORTC I/O data latch.
PIC18F2480/2580/4480/4580 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. EQUATION 16-3: PWM Resolution (max) = When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Note: The maximum PWM resolution (bits) for a given PWM frequency is given by the equation.
PIC18F2480/2580/4480/4580 TABLE 16-5: Name REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 INTCON RCON Reset Values on Page: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 IPEN SBOREN(2) — RI TO PD POR BOR 56 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 TRISB PORTB Data Dire
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 176 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 17.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE Note: The ECCP1 module is implemented only in PIC18F4X80 (40/44-pin) devices. In PIC18F4480/4580 devices, ECCP1 is implemented as a standard CCP module with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The REGISTER 17-1: Enhanced features are discussed in detail in Section 17.4 “Enhanced PWM Mode”.
PIC18F2480/2580/4480/4580 In addition to the expanded range of modes available through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (Dead-Band Delay) • ECCP1AS (Auto-Shutdown Control) 17.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
PIC18F2480/2580/4480/4580 17.4 Enhanced PWM Mode 17.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D.
PIC18F2480/2580/4480/4580 17.4.2 PWM DUTY CYCLE EQUATION 17-3: The PWM duty cycle is specified by writing to the ECCPR1L register and to the ECCP1CON<5:4> bits. Up to 10-bit resolution is available. The ECCPR1L contains the eight MSbs and the ECCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation.
PIC18F2480/2580/4480/4580 FIGURE 17-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL ECCP1CON <7:6> 00 0 PR2 + 1 Duty Cycle Period (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active P1B Inactive (Full-Bridge, Forward) 01 P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, Reverse) 11 P1C Active P1D Inactive FIGURE 17-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) ECCP1CON <7:6> 00 (Single Output) SIGNAL 0 P
PIC18F2480/2580/4480/4580 17.4.4 HALF-BRIDGE MODE FIGURE 17-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 17-4). This mode can be used for half-bridge applications, as shown in Figure 17-5, or for full-bridge applications where four power switches are being modulated with two PWM signals.
PIC18F2480/2580/4480/4580 17.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 17-6. FIGURE 17-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<5>, PORTD<6> and PORTD<7> data latches.
PIC18F2480/2580/4480/4580 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION V+ PIC18F2X80/4X80 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 17.4.5.1 Direction Change in Full-Bridge Output Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F2480/2580/4480/4580 FIGURE 17-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F2480/2580/4480/4580 17.4.6 Note: PROGRAMMABLE DEAD-BAND DELAY Programmable dead-band delay is not implemented in PIC18F2X80 devices with standard CCP modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on.
PIC18F2480/2580/4480/4580 REGISTER 17-2: ECCP1DEL: ECCP PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
PIC18F2480/2580/4480/4580 17.4.7.1 Auto-Shutdown and Auto-Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 17-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared.
PIC18F2480/2580/4480/4580 17.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. 2. 3. 4. 5. 6. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 register.
PIC18F2480/2580/4480/4580 TABLE 17-3: Name INTCON RCON REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Values on Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 IPEN SBOREN — RI TO PD POR BOR 56 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 (3) (3
PIC18F2480/2580/4480/4580 18.0 18.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F2480/2580/4480/4580 18.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F2480/2580/4480/4580 REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmittin
PIC18F2480/2580/4480/4580 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F2480/2580/4480/4580 18.3.3 ENABLING SPI I/O 18.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F2480/2580/4480/4580 18.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 18-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18F2480/2580/4480/4580 18.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>).
PIC18F2480/2580/4480/4580 FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 bit 6 bit
PIC18F2480/2580/4480/4580 18.3.8 OPERATION IN POWER-MANAGED MODES 18.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the Sleep mode, all clocks are halted. In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 3.
PIC18F2480/2580/4480/4580 18.4 I2C Mode 18.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F2480/2580/4480/4580 REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled f
PIC18F2480/2580/4480/4580 REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C
PIC18F2480/2580/4480/4580 REGISTER 18-5: R/W-0 GCEN SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 ACKSTAT ACKDT(1) R/W-0 (2) ACKEN R/W-0 (2) RCEN R/W-0 (2) PEN R/W-0 (2) RSEN R/W-0 SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received i
PIC18F2480/2580/4480/4580 18.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F2480/2580/4480/4580 18.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set, or bit, SSPOV (SSPCON1<6>), is set.
DS39637D-page 206 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPCON1<4>) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
© 2009 Microchip Technology Inc.
DS39637D-page 208 2 1 3 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated 8 9 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPCON1<4>) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) 6 A9 SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 5 A4 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1
© 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 18.4.4 CLOCK STRETCHING Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 18.4.4.
PIC18F2480/2580/4480/4580 18.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 18-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39637D-page 212 CKP (SSPCON1<4>) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretc
© 2009 Microchip Technology Inc. 2 1 3 1 4 1 5 0 CKP (SSPCON1<4>) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F2480/2580/4480/4580 18.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F2480/2580/4480/4580 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F2480/2580/4480/4580 18.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
PIC18F2480/2580/4480/4580 18.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 18-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F2480/2580/4480/4580 18.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 18-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F2480/2580/4480/4580 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18F2480/2580/4480/4580 18.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
PIC18F2480/2580/4480/4580 18.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39637D-page 222 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting D
© 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 18.4.12 ACKNOWLEDGE SEQUENCE TIMING 18.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F2480/2580/4480/4580 18.4.14 SLEEP OPERATION 18.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 18.4.15 Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high, and another master asserts a ‘0’.
PIC18F2480/2580/4480/4580 18.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL is sampled low at the beginning of the Start condition (Figure 18-26). SCL is sampled low before SDA is asserted low (Figure 18-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 18-28).
PIC18F2480/2580/4480/4580 FIGURE 18-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F2480/2580/4480/4580 18.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 18-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-tolow before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F2480/2580/4480/4580 18.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 18-31).
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 230 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 19.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F2480/2580/4480/4580 REGISTER 19-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F2480/2580/4480/4580 REGISTER 19-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset)
PIC18F2480/2580/4480/4580 REGISTER 19-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG
PIC18F2480/2580/4480/4580 19.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F2480/2580/4480/4580 EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F2480/2580/4480/4580 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.
PIC18F2480/2580/4480/4580 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.
PIC18F2480/2580/4480/4580 19.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F2480/2580/4480/4580 FIGURE 19-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h RX Pin 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F2480/2580/4480/4580 19.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first.
PIC18F2480/2580/4480/4580 FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) Pin Buffer and Control 0 • • • TSR Register TX Pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPBRG TX9 TX9D Baud Rate Generator FIGURE 19-4: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TX (pin) Start bit FIGURE 19-5: bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg.
PIC18F2480/2580/4480/4580 TABLE 19-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 (1) PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 58 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 58 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 57
PIC18F2480/2580/4480/4580 19.2.2 EUSART ASYNCHRONOUS RECEIVER 19.2.3 The receiver block diagram is shown in Figure 19-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F2480/2580/4480/4580 FIGURE 19-7: ASYNCHRONOUS RECEPTION Start bit bit 0 RX (pin) bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: TABLE 19-6: Name This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set.
PIC18F2480/2580/4480/4580 19.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
PIC18F2480/2580/4480/4580 19.2.5 BREAK CHARACTER SEQUENCE The Enhanced EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F2480/2580/4480/4580 19.3 EUSART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18F2480/2580/4480/4580 FIGURE 19-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 19-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 55 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 58 PIE1 PSPIE(1) A
PIC18F2480/2580/4480/4580 19.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F2480/2580/4480/4580 19.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.4.1 EUSART SYNCHRONOUS SLAVE TRANSMIT 2. 3. 4. 5. 6.
PIC18F2480/2580/4480/4580 19.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F2480/2580/4480/4580 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 8 inputs for the PIC18F2X80 devices and 11 for the PIC18F4X80 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
PIC18F2480/2580/4480/4580 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W-q(1) R/W-q(1) R/W-q(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG<3:0> AN4 AN3 AN2 AN1 AN0 PCFG<3:0>: A/D Port Configuration Control bits: AN5(2) bit 3-0 AN6(2) VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VR
PIC18F2480/2580/4480/4580 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 T
PIC18F2480/2580/4480/4580 The analog reference voltage is software-selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input, or as a digital I/O.
PIC18F2480/2580/4480/4580 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 “A/D Acquisition Requirements”.
PIC18F2480/2580/4480/4580 20.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F2480/2580/4480/4580 20.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F2480/2580/4480/4580 20.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part, by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started.
PIC18F2480/2580/4480/4580 20.6 A/D Conversions Figure 20-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC18F2480/2580/4480/4580 20.7 Use of the CCP1 Trigger An A/D conversion can be started by the “Special Event Trigger” of the ECCP1 module. This requires that the ECCP1M<3:0> bits (ECCP1CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero.
PIC18F2480/2580/4480/4580 21.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins, RA0 through RA5, as well as the on-chip voltage reference (see Section 22.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
PIC18F2480/2580/4480/4580 21.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 21-1. Bits, CM<2:0> of the CMCON register, are used to select these modes. The TRISA register controls the data direction of the comparator pins for each mode.
PIC18F2480/2580/4480/4580 21.2 Comparator Operation 21.3.2 A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
PIC18F2480/2580/4480/4580 + To RE1 or RE2 Pin - Port Pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 21-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From other Comparator Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F2480/2580/4480/4580 21.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 21-4.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 268 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 22.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram is of the module shown in Figure 22-1.
PIC18F2480/2580/4480/4580 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16 to 1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 22.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 22-1) keep CVREF from approaching the reference source rails.
PIC18F2480/2580/4480/4580 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F4X80 CVREF Module R(1) Voltage Reference Output Impedance + – RA0 CVREF Output Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 272 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 23.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F2480/2580/4480/4580 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set.
PIC18F2480/2580/4480/4580 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. level at which the device detects a high or low-voltage event, depending on the configuration of the module.
PIC18F2480/2580/4480/4580 23.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>).
PIC18F2480/2580/4480/4580 FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, the ability to detect a drop below, or rise above a particular threshol
PIC18F2480/2580/4480/4580 23.6 Operation During Sleep 23.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 278 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 24.0 ECAN MODULE PIC18F2480/2580/4480/4580 devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices. This interface, or protocol, was designed to allow communications within noisy environments.
PIC18F2480/2580/4480/4580 BUFFERS 16 - 4 to 1 MUXs MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF MSGREQ ABTF MLOA TXERR MTXBUFF TXB2 MESSAGE TXB1 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB0 A c c e p t Acceptance Filters (RXF0-RXF05) MODE 0 Acceptance Filters (RXF06-RXF15) MODE 1, 2 MODE 0 2 RX Buffers Message Queue Control Transmit Byte Sequencer VCC Acceptance Mask RXM0 CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 FIGURE 24-1: RXF15 Identifier Data Field M A B Rcv Byte
PIC18F2480/2580/4480/4580 24.2 Note: CAN Module Registers Not all CAN registers are available in the Access Bank. There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: • • • • • • • 24.2.1 CAN CONTROL AND STATUS REGISTERS The registers described in this section control the overall operation of the CAN module and show its operational status.
PIC18F2480/2580/4480/4580 REGISTER 24-1: Mode 0 Mode 1 Mode 2 CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0 REQOP2 REQOP1 REQOP0 ABAT — — — — R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC18F2480/2580/4480/4580 REGISTER 24-2: Mode 0 Mode 1,2 CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 (1) (1) OPMODE2 OPMODE1 OPMODE0(1) R-0 — R-0 ICODE3 R-1 R-0 R-0 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set R-0 ICODE2 R-0 ICODE1 R-0 EICODE2 R-0 EICODE1 U-0 — R-0 EICODE0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OPMODE<2:0>: Operation Mode Status bits(1) 111 = R
PIC18F2480/2580/4480/4580 EXAMPLE 24-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing.
PIC18F2480/2580/4480/4580 EXAMPLE 24-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error.
PIC18F2480/2580/4480/4580 REGISTER 24-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 MDSEL<1:0>: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mod
PIC18F2480/2580/4480/4580 REGISTER 24-4: Mode 0 Mode 1 Mode 2 COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 FIFOEMPTY RXBnOVFL R-0 R-0 R-0 R-0 R-0 R-0 TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit
PIC18F2480/2580/4480/4580 24.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers.
PIC18F2480/2580/4480/4580 REGISTER 24-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits EID<28:21>
PIC18F2480/2580/4480/4580 REGISTER 24-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 2
PIC18F2480/2580/4480/4580 REGISTER 24-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted m
PIC18F2480/2580/4480/4580 EXAMPLE 24-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access.
PIC18F2480/2580/4480/4580 24.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers.
PIC18F2480/2580/4480/4580 REGISTER 24-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits<4:0>.
PIC18F2480/2580/4480/4580 REGISTER 24-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER Mode 0 Mode 1,2 R/C-0 RXFUL(1) R/W-0 RXM1 R/W-0 RXM0 U-0 — R-0 RXRTRRO R/W-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 R/C-0 RXFUL(1) bit 7 R/W-0 RXM1 R-0 RTRRO R-0 FILHIT4 R-0 FILHIT3 R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is clea
PIC18F2480/2580/4480/4580 REGISTER 24-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Note 1: Mode 0: FILHIT<2:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.
PIC18F2480/2580/4480/4580 REGISTER 24-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1).
PIC18F2480/2580/4480/4580 REGISTER 24-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserv
PIC18F2480/2580/4480/4580 REGISTER 24-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown REC<7:0>: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications.
PIC18F2480/2580/4480/4580 24.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0.
PIC18F2480/2580/4480/4580 REGISTER 24-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 1](1) R/W-0 TXBIF R-0 (3) TXABT R-0 (3) TXLARB R-0 (3) R/W-0 (3) TXERR TXREQ (2,4) R/W-0 RTREN R/W-0 TXPRI1 (5) R/W-0 TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message
PIC18F2480/2580/4480/4580 REGISTER 24-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended I
PIC18F2480/2580/4480/4580 REGISTER 24-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18>
PIC18F2480/2580/4480/4580 REGISTER 24-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID<15:8>: Extended Identifier bits These registers are available in
PIC18F2480/2580/4480/4580 REGISTER 24-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID<7:0>: Extended Identifier bits These registers are availa
PIC18F2480/2580/4480/4580 REGISTER 24-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request
PIC18F2480/2580/4480/4580 REGISTER 24-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will hav
PIC18F2480/2580/4480/4580 24.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers.
PIC18F2480/2580/4480/4580 REGISTER 24-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID<15:8>: Extended Identifier Filter bits Registers, RXF6EIDH:RXF15EIDH, a
PIC18F2480/2580/4480/4580 REGISTER 24-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0 ≤ n ≤ 1] R/W-x R/W-x SID2 SID1 R/W-x SID0 U-0 — R/W-0 (1) EXIDEN U-0 R/W-x R/W-x — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>) bit 4 U
PIC18F2480/2580/4480/4580 REGISTER 24-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1](1) RXFCON0 RXFCON1 R/W-0 RXF7EN R/W-0 RXF6EN R/W-1 RXF5EN R/W-1 RXF4EN R/W-1 RXF3EN R/W-1 RXF2EN R/W-1 RXF1EN R/W-1 RXF0EN R/W-0 RXF15EN bit 7 R/W-0 RXF14EN R/W-0 RXF13EN R/W-1 R/W-0 RXF12EN RXF11EN R/W-0 RXF10EN R/W-0 RXF9EN R/W-0 RXF8EN bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: Note: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cl
PIC18F2480/2580/4480/4580 REGISTER 24-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1) RXFBCON0 R/W-0 F1BP_3 R/W-0 F1BP_2 R/W-0 F1BP_1 R/W-0 F1BP_0 R/W-0 F0BP_3 R/W-0 F0BP_2 R/W-0 F0BP_1 R/W-0 F0BP_0 RXFBCON1 R/W-0 F3BP_3 R/W-0 F3BP_2 R/W-0 F3BP_1 R/W-1 F3BP_0 R/W-0 F2BP_3 R/W-0 F2BP_2 R/W-0 F2BP_1 R/W-1 F2BP_0 RXFBCON2 R/W-0 F5BP_3 R/W-0 F5BP_2 R/W-0 F5BP_1 R/W-1 F5BP_0 R/W-0 F4BP_3 R/W-0 F4BP_2 R/W-0 F4BP_1 R/W-1 F4BP_0 RXFBCON3 R/W-0 F7BP_3 R/W-0 F7BP_2 R/W-0 F7BP_1
PIC18F2480/2580/4480/4580 REGISTER 24-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL3_<1:0>: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_<1:0>: Filter 2 Select bi
PIC18F2480/2580/4480/4580 REGISTER 24-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL7_<1:0>: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_<1:0>: Filter 6 Select bi
PIC18F2480/2580/4480/4580 REGISTER 24-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL11_<1:0>: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_<1:0>: Filter 10 S
PIC18F2480/2580/4480/4580 REGISTER 24-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL15_<1:0>: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_<1:0>: Filter
PIC18F2480/2580/4480/4580 24.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are Configuration mode only.
PIC18F2480/2580/4480/4580 REGISTER 24-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), which
PIC18F2480/2580/4480/4580 REGISTER 24-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 WAKDIS WAKFIL U-0 — U-0 U-0 — — R/W-0 SEG2PH2 R/W-0 (1) SEG2PH1 R/W-0 (1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter
PIC18F2480/2580/4480/4580 24.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller.
PIC18F2480/2580/4480/4580 24.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 10.0 “Interrupts”. They are duplicated here for convenience.
PIC18F2480/2580/4480/4580 REGISTER 24-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 Mode 0 Mode 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE(1) TXB0IE(1) RXB1IE RXB0IE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXBnIE TXB1IE(1) TXB0IE(1) RXBnIE FIFOWMIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
PIC18F2480/2580/4480/4580 REGISTER 24-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 Mode 0 Mode 1,2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXBnIP TXB1IP(1) TXB0IP(1) RXBnIP FIFOWMIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit
PIC18F2480/2580/4480/4580 REGISTER 24-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE(2) TXB1IE(2) TXB0IE(2) — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer int
PIC18F2480/2580/4480/4580 TABLE 24-1: Address(1) CAN CONTROLLER REGISTER MAP Name Address Name Address Name Address Name F7Fh SPBRGH(3) F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh —(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch —(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh —(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah (4) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F58h RXB1D2 F38h TXB1D2 F18h RX
PIC18F2480/2580/4480/4580 TABLE 24-1: Address(1) CAN CONTROLLER REGISTER MAP (CONTINUED) Name EFFh —(4) Address Name EDFh —(4) EFEh — (4) EFDh —(4) EFCh — (4) EFBh —(4) EFAh (4) Address Name Address Name EBFh —(4) E9Fh —(4) EDEh (4) — EBEh — (4) E9Eh —(4) EDDh —(4) EBDh —(4) E9Dh —(4) EDCh — (4) EBCh — (4) E9Ch —(4) EDBh —(4) EBBh —(4) E9Bh —(4) — EDAh (4) — EBAh — (4) E9Ah —(4) EF9h —(4) ED9h —(4) EB9h —(4) E99h —(4) EF8h (4) — ED8
PIC18F2480/2580/4480/4580 TABLE 24-1: Address(1) CAN CONTROLLER REGISTER MAP (CONTINUED) Name Address Name Address Name Address Name E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh —(4) (2) (2) (2) E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E3Eh CANSTAT_RO8 E1Eh —(4) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(4) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(4) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(4) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(4) E79h B5D3 E59h B3D3 E3
PIC18F2480/2580/4480/4580 TABLE 24-1: Address(1) CAN CONTROLLER REGISTER MAP (CONTINUED) Name DFFh —(4) Address Name DDFh —(4) DFEh — (4) DFDh —(4) Address Name Address Name DBFh —(4) D9Fh —(4) DDEh — (4) DBEh — (4) D9Eh —(4) DDDh —(4) DBDh —(4) D9Dh —(4) (4) DBCh — (4) D9Ch —(4) DFCh TXBIE DDCh — DFBh —(4) DDBh —(4) DBBh —(4) D9Bh —(4) (4) DBAh — (4) D9Ah —(4) DB9h —(4) D99h —(4) (4) DFAh BIE0 DDAh — DF9h —(4) DD9h —(4) DF8h BSEL0 DD
PIC18F2480/2580/4480/4580 TABLE 24-1: Address(1) CAN CONTROLLER REGISTER MAP (CONTINUED) Name D7Fh —(4) D7Eh —(4) D7Dh —(4) D7Ch —(4) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh —(4) D6Eh —(4) D6Dh —(4) D6Ch —(4) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RX
PIC18F2480/2580/4480/4580 24.3 CAN Modes of Operation The PIC18F2480/2580/4480/4580 has six main modes of operation: • • • • • • Configuration mode Disable/Sleep mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>). Error Recognition mode is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits.
PIC18F2480/2580/4480/4580 24.3.4 LISTEN ONLY MODE Listen Only mode provides a means for the PIC18F2480/2580/4480/4580 devices to receive all messages, including messages with errors. This mode can be used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations. For auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other.
PIC18F2480/2580/4480/4580 24.4.3 MODE 2 – ENHANCED FIFO MODE In Mode 2, two or more receive buffers are used to form the receive FIFO (first in, first out) buffer. There is no one-to-one relationship between the receive buffer and acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate acceptance and cause FIFO to be updated. FIFO length is user-programmable, from 2-8 buffers deep.
PIC18F2480/2580/4480/4580 24.5.4 PROGRAMMABLE AUTO-RTR BUFFERS In Mode 1 and 2, any of six programmable transmit/ receive buffers may be programmed to automatically respond to predefined RTR messages without user firmware intervention. Automatic RTR handling is enabled by setting the TXnEN bit in the BSEL0 register and the RTREN bit in the BnCON register.
PIC18F2480/2580/4480/4580 TRANSMIT PRIORITY The transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If the TXP bits for a particular message buffer are set to ‘11’, that buffer has the highest possible priority. If the TXP bits for a particular message buffer are set to ‘00’, that buffer has the lowest possible priority.
PIC18F2480/2580/4480/4580 24.7 24.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted.
PIC18F2480/2580/4480/4580 24.7.3 ENHANCED FIFO MODE When configured for Mode 2, two of the dedicated receive buffers in combination with one or more programmable transmit/receive buffers, are used to create a maximum of an 8 buffer deep FIFO buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter that has been enabled can generate an acceptance.
PIC18F2480/2580/4480/4580 In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing the RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers.
PIC18F2480/2580/4480/4580 24.9 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock.
PIC18F2480/2580/4480/4580 24.9.1 EXTERNAL CLOCK, INTERNAL CLOCK AND MEASURABLE JITTER IN HS-PLL BASED OSCILLATORS The microcontroller clock frequency generated from a PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced microcontrollers, Microchip specifies phase jitter (Pjitter) as being 2% (Gaussian distribution, within 3 standard deviations, see parameter F13 in Table 28-7) and Total Jitter (Tjitter) as being 2*Pjitter.
PIC18F2480/2580/4480/4580 Table 24-3 shows the relation between the clock generated by the PLL and the frequency error from jitter (measured jitter-induced error of 2%, Gaussian distribution, within 3 standard deviations), as a percentage of the nominal clock frequency. TABLE 24-3: PLL Output This is clearly smaller than the expected drift of a crystal oscillator, typically specified at 100 ppm or 0.01%. If we add jitter to oscillator drift, we have a total frequency drift of 0.0132%.
PIC18F2480/2580/4480/4580 24.9.2 TIME QUANTA 24.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 24-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 24-6: 24.9.
PIC18F2480/2580/4480/4580 24.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2 as necessary.
PIC18F2480/2580/4480/4580 FIGURE 24-6: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Time Segments Sync Prop Segment Phase Segment 1 Phase Segment 2 ≤ SJW TQ Sample Point Nominal Bit Length Actual Bit Length FIGURE 24-7: Sync SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Segment Phase Segment 1 TQ Phase Segment 2 ≤ SJW Sample Point Actual Bit Length Nominal Bit Length 24.
PIC18F2480/2580/4480/4580 24.13 Bit Timing Configuration Registers The Baud Rate Control registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18F2480/2580/4480/4580 devices are in Configuration mode. 24.13.1 BRGCON1 The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. 24.13.2 BRGCON2 24.14.
PIC18F2480/2580/4480/4580 The PIC18F2480/2580/4480/4580 devices are erroractive if both error counters are below the error-passive limit of 128. They are error-passive if at least one of the error counters equals or exceeds 128. They go to busoff if the transmit error counter equals or exceeds the bus-off limit of 256. The devices remain in this state until the bus-off recovery sequence is finished. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 24-8).
PIC18F2480/2580/4480/4580 24.15.1 INTERRUPT CODE BITS To simplify the interrupt handling process in user firmware, the ECAN module encodes a special set of bits. In Mode 0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower values.
PIC18F2480/2580/4480/4580 24.15.6.1 Receiver Overflow An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated RXBnOVFL bit in the COMSTAT register will be set to indicate the overflow condition. This bit must be cleared by the MCU. 24.15.6.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 348 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 25.0 SPECIAL FEATURES OF THE CPU The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays.
PIC18F2480/2580/4480/4580 REGISTER 25-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabl
PIC18F2480/2580/4480/4580 REGISTER 25-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits 11 = VBOR set to 2.1V 10 = VBOR set to 2.
PIC18F2480/2580/4480/4580 REGISTER 25-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 =
PIC18F2480/2580/4480/4580 REGISTER 25-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 U-0 MCLRE — — — — LPT1OSC PBADEN — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Re
PIC18F2480/2580/4480/4580 REGISTER 25-6: U-0 CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 — — U-0 — U-0 — R/C-1 R/C-1 (1) (1) CP3 CP2 R/C-1 R/C-1 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code-protected 0 = Block 3 (006000-007FFFh)
PIC18F2480/2580/4480/4580 REGISTER 25-8: U-0 CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 — — U-0 U-0 — — R/C-1 WRT3 (1) R/C-1 (1) WRT2 R/C-1 R/C-1 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write-protected 0 = Block 3 (006000-00
PIC18F2480/2580/4480/4580 REGISTER 25-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1,2) EBTR2(1,2) EBTR1(2) EBTR0(2) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not protected from ta
PIC18F2480/2580/4480/4580 REGISTER 25-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2480/2580/4480/4580 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits 111 = PIC18F2480 110 = PIC18F2580 101 = PIC18F4480 100 = PIC18F4580 bit 4-0 REV<3:0>: Revision ID bits These bits are used to in
PIC18F2480/2580/4480/4580 25.2 Watchdog Timer (WDT) For PIC18F2480/2580/4480/4580 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
PIC18F2480/2580/4480/4580 REGISTER 25-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configurati
PIC18F2480/2580/4480/4580 25.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit.
PIC18F2480/2580/4480/4580 25.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F2480/2580/4480/4580 FIGURE 25-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 25.4.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
PIC18F2480/2580/4480/4580 25.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes.
PIC18F2480/2580/4480/4580 TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3* CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3* WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3* EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented.
PIC18F2480/2580/4480/4580 FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18F2480/2580/4480/4580 25.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 25.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18F2480/2580/4480/4580 26.0 INSTRUCTION SET SUMMARY PIC18F2480/2580/4480/4580 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 26.
PIC18F2480/2580/4480/4580 TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F2480/2580/4480/4580 FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 1,2 0001 01da ffff ffff Z, N CLRF Clear f f, a 1 2 0110 101a ffff ffff Z COMF f, d, a Complement f 1 1, 2 0001 11da ffff ffff Z, N
PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f BSF f, b, a Bit Set f BTFSC f, b, a Bit Test f, Skip if Clear BTFSS f, b, a Bit Test f, Skip if Set BTG f, b, a Bit Toggle f CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally
PIC18F2480/2580/4480/4580 TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Liter
PIC18F2480/2580/4480/4580 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F2480/2580/4480/4580 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F2480/2580/4480/4580 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff 1110 Description: The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F2480/2580/4480/4580 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f, b {,a} Operation: 0 → f Status Affected: None Encoding: 1001 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F2480/2580/4480/4580 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F2480/2580/4480/4580 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch.
PIC18F2480/2580/4480/4580 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18F2480/2580/4480/4580 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F2480/2580/4480/4580 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted. 0100 nnnn nnnn If the Overflow bit is ‘1’, then the program will branch.
PIC18F2480/2580/4480/4580 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F2480/2580/4480/4580 CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: 000h → f, 1→Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F2480/2580/4480/4580 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: ( f ) → dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘1’, the result is stored in W.
PIC18F2480/2580/4480/4580 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of t
PIC18F2480/2580/4480/4580 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then, (W<7:4>) + 6 → W<7:4>; C = 1, else, (W<7:4>) → W<7:4> Status Affected: 0000 Description: 0000 0000 0000 0111 Description: DAW
PIC18F2480/2580/4480/4580 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2480/2580/4480/4580 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F2480/2580/4480/4580 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F2480/2580/4480/4580 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W Status Affected: N, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F2480/2580/4480/4580 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F2480/2580/4480/4580 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 1100 1111 2nd word (destin.) Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F2480/2580/4480/4580 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F2480/2580/4480/4580 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F2480/2580/4480/4580 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operands: None Operation: No operation None Operation: (f)+1→f Status Affected: Status Affected: N, OV, C, DC, Z Encoding: Encoding: 0110 Description: 110a ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F2480/2580/4480/4580 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F2480/2580/4480/4580 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F2480/2580/4480/4580 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged.
PIC18F2480/2580/4480/4580 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subrou
PIC18F2480/2580/4480/4580 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F2480/2580/4480/4580 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Operation: (f) → dest, (f<0>) → dest<7> Status Affected: None Status Affected: Encoding: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Set f ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2480/2580/4480/4580 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down Status bit (PD) is cleared. The Time-out Status bit (TO) is set.
PIC18F2480/2580/4480/4580 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F2480/2580/4480/4580 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F2480/2580/4480/4580 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT; Status Affected: None Encoding: Description: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
PIC18F2480/2580/4480/4580 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion)
PIC18F2480/2580/4480/4580 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W N, Z Operation: skip if f = 0 Status Affected: Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F2480/2580/4480/4580 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F2480/2580/4480/4580 26.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 26-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2480/2580/4480/4580 devices also provide an optional extension to the core CPU functionality.
PIC18F2480/2580/4480/4580 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 FSR(f) + k → FSR(f) Operation: Operation: FSR2 + k → FSR2, PC = (TOS) Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F2480/2580/4480/4580 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: 0000 Description Encoding: None Encoding: 0000 Move Indexed to f 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F2480/2580/4480/4580 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: ((FSR2) + zs) → ((FSR2) + zd) Operation: k → (FSR2), FSR2 – 1→ FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 1110 1111 2nd word (dest.) Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18F2480/2580/4480/4580 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: Operation: FSRf – k → FSRf FSR2 – k → FSR2 (TOS) → PC Status Affected: None Encoding: 1110 Subtract Literal from FSR2 and Return Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F2480/2580/4480/4580 26.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F2480/2580/4480/4580 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] a=0 Operands: 0 ≤ f ≤ 95 0≤b≤7 a=0 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2 + k)) Status Affected: None [k] {,d} Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offse
PIC18F2480/2580/4480/4580 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2480/2580/4480/4580 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F2480/2580/4480/4580 27.
PIC18F2480/2580/4480/4580 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC18F2480/2580/4480/4580 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F2480/2580/4480/4580 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F2480/2580/4480/4580 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ............................................
PIC18F2480/2580/4480/4580 FIGURE 28-1: PIC18F2480/2580/4480/4580 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V PIC18F2X80/4X80 5.0V Voltage 4.5V 4.2V 4.0V 3.5V Industrial and Extended Devices 3.0V Industrial Devices Only 2.5V 2.0V 25 MHz 40 MHz Frequency FIGURE 28-2: PIC18LF2480/2580/4480/4580 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2X80/4X80 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.
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PIC18F2480/2580/4480/4580 28.
PIC18F2480/2580/4480/4580 28.
PIC18F2480/2580/4480/4580 28.
PIC18F2480/2580/4480/4580 28.
PIC18F2480/2580/4480/4580 28.
PIC18F2480/2580/4480/4580 28.3 DC Characteristics: PIC18F2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No.
PIC18F2480/2580/4480/4580 28.3 DC Characteristics: PIC18F2480/2580/4480/4580 (Industrial) PIC18LF2480/2580/4480/4580 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No.
PIC18F2480/2580/4480/4580 TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions 9.00 — 13.
PIC18F2480/2580/4480/4580 TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) -40°C < TA < +125°C for extended Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
PIC18F2480/2580/4480/4580 FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared in software) VLVD (HLVDIF set by hardware) HLVDIF TABLE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C < TA < +125°C for extended Param Symbol No. D420 Characteristic Min Typ Max Units HLVD Voltage on VDD LVV = 0000 Transition High-to-Low LVV = 0001 2.12 2.17 2.22 V 2.
PIC18F2480/2580/4480/4580 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
PIC18F2480/2580/4480/4580 28.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 28-5 apply to all timing specifications unless otherwise noted. Figure 28-4 specifies the load conditions for the timing specifications. TABLE 28-5: Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F2480/2580/4480/4580 and PIC18LF2480/2580/4480/4580 families of devices specifically and only those devices.
PIC18F2480/2580/4480/4580 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 28-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 1 MHz DC 25 MHz HS Oscillator mode DC 31.
PIC18F2480/2580/4480/4580 TABLE 28-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (lock time) — — 2 ms ΔCLK CLKO Stability (jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25°C unless otherwise stated.
PIC18F2480/2580/4480/4580 FIGURE 28-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 28-4 for load conditions. TABLE 28-9: Param No.
PIC18F2480/2580/4480/4580 FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins FIGURE 28-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 28-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No.
PIC18F2480/2580/4480/4580 FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 TABLE 28-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F2480/2580/4480/4580 FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 28-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param No. 50 Sym TCCL Characteristic CCPx Input Low No prescaler Time With prescaler PIC18FXXXX PIC18LFXXXX 51 TCCH CCPx Input High No prescaler Time With prescaler PIC18FXXXX PIC18LFXXXX 52 TCCP 53 TCCR CCPx Output Fall Time 54 TCCF © 2009 Microchip Technology Inc. Max Units 0.
PIC18F2480/2580/4480/4580 FIGURE 28-11: PARALLEL SLAVE PORT TIMING (PIC18F4480/4580) RE2/CS RE0/RD RE1/WR 65 RD<7:0> 62 64 63 TABLE 28-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4480/4580) Param. No.
PIC18F2480/2580/4480/4580 FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCK (CKP = 0) 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 28-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F2480/2580/4480/4580 FIGURE 28-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F2480/2580/4480/4580 FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI bit 6 - - - -1 LSb In 74 73 TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic Min 70 TSSL2SCH SS ↓ to SCK ↓ or SCK ↑ Input , TSSL2SCL 71 TSCH SCK Input High Time Continuous TSCL SCK Input Low Time 71A 72 72A 3 TCY — ns 1.
PIC18F2480/2580/4480/4580 FIGURE 28-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic 70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input TSSL2SCL 71 TSCH SCK Input High Time 71A 72 TSCL SCK Input Low Time 72A Min Max Units Conditions 3 TCY — ns Continuous 1.
PIC18F2480/2580/4480/4580 FIGURE 28-16: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition TABLE 28-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F2480/2580/4480/4580 TABLE 28-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 Characteristic Clock High Time Clock Low Time Min Max Units Conditions 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.7 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC18F2480/2580/4480/4580 FIGURE 28-18: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition TABLE 28-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F2480/2580/4480/4580 TABLE 28-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No.
PIC18F2480/2580/4480/4580 FIGURE 28-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK Pin 121 121 RC7/RX/DT Pin 120 122 TABLE 28-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F2480/2580/4480/4580 TABLE 28-24: A/D CONVERTER CHARACTERISTICS: PIC18F2480/2580/4480/4580 (INDUSTRIAL) PIC18LF2480/2580/4480/4580 (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units — — 10 bit Conditions ΔVREF ≥ 3.0V A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.
PIC18F2480/2580/4480/4580 FIGURE 28-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 458 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP Example PIC18F2580-I/SP e3 0910017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC18F2480/2580/4480/4580 29.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39637D-page 460 PIC18F4580-I/P e3 0910017 Example PIC18F4580 -I/PT e3 0910017 Example PIC18F4580 -I/ML e3 0910017 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 29.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC18F2480/2580/4480/4580 # # $ % &'( # ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 L1 6 &! ' ! 9 ' &! 7"') % ! β 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& .
PIC18F2480/2580/4480/4580 * + % ! , - ./. *+! 0 1 '(( ) , 1 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC18F2480/2580/4480/4580 * + % ! , - ./. *+! 0 1 '(( ) , 1 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS39637D-page 464 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 2 . ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC18F2480/2580/4480/4580 22 31 ! " * + 4 3 5 /5 /5 % ' 3*+ 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 6 &! ' ! 9 ' &! 7"') % 9 #! A2 L1 99 . .
PIC18F2480/2580/4480/4580 22 31 ! " * + 4 3 5 /5 /5 % ' 3*+ 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 22 * + % ! , - / *+! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & < & # %% , & & 4 !! - : > #& . .
PIC18F2480/2580/4480/4580 22 * + % ! , - / *+! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 470 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 APPENDIX A: REVISION HISTORY Revision A (July 2004) Original data sheet for PIC18F2480/2580/4480/4580 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (August 2006) Edits to Table 6-1 in Section 6.0 “Memory Organization” and trademarking updated. Revision C (March 2007) Edits to Table 6-1 in Section 6.0 “Memory Organization”, pin name change in Section 22.
PIC18F2480/2580/4480/4580 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.
PIC18F2480/2580/4480/4580 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 474 © 2009 Microchip Technology Inc.
PIC18F2480/2580/4480/4580 INDEX A A/D ................................................................................... 253 A/D Converter Interrupt, Configuring ....................... 257 Acquisition Requirements ........................................ 258 ADCON0 Register .................................................... 253 ADCON1 Register .................................................... 253 ADCON2 Register .................................................... 253 ADRESH Register ................
PIC18F2480/2580/4480/4580 BSF .................................................................................. 379 BTFSC ............................................................................. 380 BTFSS .............................................................................. 380 BTG .................................................................................. 381 BZ ..................................................................................... 382 C C Compilers MPLAB C18 .........
PIC18F2480/2580/4480/4580 Write Verify .............................................................. 113 Writing ...................................................................... 113 Data Memory ..................................................................... 73 Access Bank .............................................................. 76 and the Extended Instruction Set ............................... 98 Bank Select Register (BSR) .......................................
PIC18F2480/2580/4480/4580 Error Recognition Mode ................................................... 330 EUSART Asynchronous Mode ................................................ 241 Associated Registers, Receive ........................ 245 Associated Registers, Transmit ....................... 243 Auto-Wake-up on Sync Break .......................... 246 Break Character Sequence .............................. 247 Receiver ...........................................................
PIC18F2480/2580/4480/4580 Indexed Literal Offset Addressing Mode .......................... 414 and Standard PIC18 Instructions ............................. 414 Indexed Literal Offset Mode ....................................... 98, 100 Indirect Addressing ............................................................ 96 INFSNZ ............................................................................ 389 Initialization Conditions for all Registers ...................... 55–66 Instruction Cycle ...........
PIC18F2480/2580/4480/4580 Memory Organization ......................................................... 67 Data Memory ............................................................. 73 Program Memory ....................................................... 67 Memory Programming Requirements .............................. 435 Microchip Internet Web Site ............................................. 486 Migration from Baseline to Enhanced Devices ................
PIC18F2480/2580/4480/4580 PORTB Associated Registers ............................................... 140 I/O Summary ............................................................ 139 LATB Register .......................................................... 138 PORTB Register ...................................................... 138 TRISB Register ........................................................ 138 PORTC Associated Registers ............................................... 142 I/O Summary ............
PIC18F2480/2580/4480/4580 RC_IDLE Mode .................................................................. 45 RC_RUN Mode .................................................................. 41 RCALL .............................................................................. 397 RCON Register Bit Status During Initialization .................................... 54 Reader Response ............................................................ 487 Receiver Warning ...............................................
PIC18F2480/2580/4480/4580 STATUS ..................................................................... 94 STKPTR (Stack Pointer) ............................................ 69 T0CON (Timer0 Control) .......................................... 151 T1CON (Timer 1 Control) ......................................... 155 T2CON (Timer2 Control) .......................................... 161 T3CON (Timer3 Control) .......................................... 163 TRISE (PORTE/PSP Control) .............................
PIC18F2480/2580/4480/4580 PR2 Register .................................................... 173, 179 TMR2 to PR2 Match Interrupt .......................... 173, 179 Timer3 .............................................................................. 163 16-Bit Read/Write Mode ........................................... 165 Associated Registers ....................................... 165, 172 Operation ................................................................. 164 Oscillator .........................
PIC18F2480/2580/4480/4580 Example SPI Mode Requirements Master Mode, CKE = 0 .................................... 447 Master Mode, CKE = 1 .................................... 448 Slave Mode, CKE = 0 ...................................... 449 Slave Mode, CKE = 1 ...................................... 450 External Clock Requirements .................................. 440 High/Low-Voltage Detect Characteristics ................ 437 I2C Bus Data Requirements (Slave Mode) ..............
PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 486 © 2009 Microchip Technology Inc.
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PIC18F2480/2580/4480/4580 PIC18F2480/2580/4480/4580 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2480/2580(1), PIC18F4480/4580 (1), PIC18F2480/2580T (2), PIC18F4480/4580T (2); VDD range 4.2V to 5.5V PIC18LF2480/2580(1), PIC18LF4480/4580(1), PIC18LF2480/25800T(2), PIC18LF4480/4580T(2); VDD range 2.0V to 5.
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