Datasheet

PIC18F2458/2553/4458/4553
DS39887C-page 30 © 2009 Microchip Technology Inc.
2.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE
bit will be set, starting the A/D acquisition and
conversion, and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate T
ACQ
time selected before the Special Event Trigger sets the
GO/DONE
bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
(4)
PIR1
SPPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
(4)
PIE1 SPPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
(4)
IPR1 SPPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
(4)
PIR2
OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF
(4)
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE
(4)
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP
(4)
ADRESH A/D Result Register High Byte
(4)
ADRESL A/D Result Register Low Byte
(4)
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 21
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 22
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 23
PORTA —RA6
(2)
RA5 RA4 RA3 RA2 RA1 RA0
(4)
TRISA — TRISA6
(2)
PORTA Data Direction Control Register
(4)
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
(4)
TRISB PORTB Data Direction Control Register
(4)
LATB PORTB Data Latch Register (Read and Write to Data Latch)
(4)
PORTE
(1)
RDPU — — —RE3
(3)
RE2
(1)
RE1
(1)
RE0
(1) (4)
TRISE
(1)
— — — — — TRISE2 TRISE1 TRISE0
(4)
LATE
(1)
— — — — — PORTE Data Latch Register
(4)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.