PIC18F2458/2553/4458/4553 Data Sheet 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc.
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PIC18F2458/2553/4458/4553 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology Universal Serial Bus Features: Flexible Oscillator Structure: • USB V2.0 Compliant • Low Speed (1.
PIC18F2458/2553/4458/4553 Pin Diagrams MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1)/UOE RC2/CCP1 VUSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18F2458 PIC18F2553 28-Pin SPDIP, SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2(1)/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA VDD VSS RC7/RX/DT/SDO RC
PIC18F2458/2553/4458/4553 1 2 3 4 5 6 7 8 9 10 11 PIC18F4458 PIC18F4553 33 32 31 30 29 28 27 26 25 24 23 NC/ICRST(2)/ICVPP(2) RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI VSS VDD RE2/AN7/OESPP RE1/AN6/CK2SPP RE0/AN5/CK1SPP RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT/RCV RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3/SPP3 RD2/SPP2 RD1/SPP1 RD0/SPP0 VUSB RC2/CCP1/P1A RC1/T1OSI/CCP2(1)/UOE RC0/T1OSO/T13CKI NC/ICCK(2)/ICPGC(2) NC/ICDT(2)/ICPGD(2) RB4/AN11/KBI0/CSSPP RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0
PIC18F2458/2553/4458/4553 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 21 3.0 Special Features of the CPU ....................................................................
PIC18F2458/2553/4458/4553 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2458 • PIC18F4458 • PIC18F2553 • PIC18F4553 Note: This data sheet documents only the devices’ features and specifications that are in addition to the features and specifications of the PIC18F2455/2550/4455/4550 devices.
PIC18F2458/2553/4458/4553 TABLE 1-1: DEVICE FEATURES Features Operating Frequency PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553 DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 24576 32768 24576 32768 Program Memory (Instructions) 12288 16384 12288 16384 Data Memory (Bytes) 2048 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D
PIC18F2458/2553/4458/4553 FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic PORTA Data Memory (2 Kbytes) PCLATU PCLATH 21 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch Program Memory (24/32 Kbytes) STKPTR Data Latch 8 Instruction Bus <16> RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO/RA6 Data Latch 8 4 Access Bank 12 FSR0 FSR1 FSR
PIC18F2458/2553/4458/4553 FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Memory (2 Kbytes) PCLATU PCLATH 21 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch Program Memory (24/32 Kbytes) STKPTR Data Latch 8 Instruction Bus <16> RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO/RA6 Data Latch 8 8 inc/dec logic PORTA 12 FSR0 FSR1 FSR2 PORTB RB0
PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type I ST P I ST I I Analog Analog O — CLKO O — RA6 I/O TTL Pin Name SPDIP, SOIC MCLR/VPP/RE3 MCLR 1 VPP RE3 OSC1/CLKI OSC1 CLKI 9 OSC2/CLKO/RA6 OSC2 10 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number SPDIP, SOIC Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT/RCV RA4 T0CKI C1OUT RCV 6 RA5/AN4/SS/ HLVDIN/C2OUT RA5 AN4 SS HLVDIN C2OUT 7 RA6 — I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1.
PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number SPDIP, SOIC Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number SPDIP, SOIC Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI/CCP2/UOE RC1 T1OSI CCP2(2) UOE 12 RC2/CCP1 RC2 CCP1 13 RC4/D-/VM RC4 DVM 15 RC5/D+/VP RC5 D+ VP 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT/SDO RC7 RX DT SDO 18 RE3 — VUSB 14 I/O O I ST — ST Digital I/O. Timer1 oscillator output.
PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number Pin Buffer PDIP QFN TQFP Type Type 1 18 18 I ST P I ST I I Analog Analog O — CLKO O — RA6 I/O TTL VPP RE3 OSC1/CLKI OSC1 CLKI 13 OSC2/CLKO/RA6 OSC2 14 32 33 30 31 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.
PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP QFN TQFP Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/ CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT/ RCV RA4 T0CKI C1OUT RCV 6 RA5/AN4/SS/ HLVDIN/C2OUT RA5 AN4 SS HLVDIN C2OUT 7 RA6 — 19 20 21 22 23 24 — 19 I/O I TTL Analog Digital I/O. Analog input 0.
PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 RC1/T1OSI/CCP2/ UOE RC1 T1OSI CCP2(2) UOE 16 RC2/CCP1/P1A RC2 CCP1 P1A 17 RC4/D-/VM RC4 DVM 23 RC5/D+/VP RC5 D+ VP 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT/SDO RC7 RX DT SDO 26 34 35 36 42 43 44 1 32 I/O O I ST — ST I/O I I/O O ST CMOS ST — Digital I/O.
PIC18F2458/2553/4458/4553 TABLE 1-3: Pin Name PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP QFN TQFP Description PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). PORTD can be software programmed for internal weak pull-ups on all inputs. These pins have TTL input buffers when the SPP module is enabled.
PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP QFN TQFP Description PORTE is a bidirectional I/O port. RE0/AN5/CK1SPP RE0 AN5 CK1SPP 8 RE1/AN6/CK2SPP RE1 AN6 CK2SPP 9 RE2/AN7/OESPP RE2 AN7 OESPP 10 27 I/O I O ST Analog — Digital I/O. Analog input 5. SPP clock 1 output. I/O I O ST Analog — Digital I/O. Analog input 6. SPP clock 2 output. I/O I O ST Analog — Digital I/O. Analog input 7.
PIC18F2458/2553/4458/4553 2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 10 inputs for the 28-pin devices and 13 for the 40-pin and 44-pin devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number. The ADCON0 register, shown in Register 2-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 2-2, configures the functions of the port pins.
PIC18F2458/2553/4458/4553 REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG3: PCFG0 AN5(2) AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN6(2) bit 3-0 AN7(2) VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 =
PIC18F2458/2553/4458/4553 REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20
PIC18F2458/2553/4458/4553 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O.
PIC18F2458/2553/4458/4553 Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. 6. 7.
PIC18F2458/2553/4458/4553 2.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 2-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F2458/2553/4458/4553 2.2 Selecting and Configuring Acquisition Time 2.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 13 TAD per 12-bit conversion. The source of the A/D conversion clock is software selectable.
PIC18F2458/2553/4458/4553 2.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used.
PIC18F2458/2553/4458/4553 2.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TCY wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 2-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
PIC18F2458/2553/4458/4553 2.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero.
PIC18F2458/2553/4458/4553 3.0 SPECIAL FEATURES OF THE CPU Note: 3.1 For additional details on the Configuration bits, refer to the “PIC18F2455/2550/4455/4550 Data Sheet”, Section 25.1 “Configuration Bits”. Device ID information presented in this section is for PIC18F2458/2553/4458/4553 only. Device ID Registers The Device ID registers are “read-only” registers. They identify the device type and revision to device programmers, and can be read by firmware using table reads.
PIC18F2458/2553/4458/4553 REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits See Register 3-2 for a complete listing.
PIC18F2458/2553/4458/4553 4.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) .............................................
PIC18F2458/2553/4458/4553 FIGURE 4-1: PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2458/2553/4458/4553 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 48 MHz Frequency FIGURE 4-2: PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF2458/2553/4458/4553 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz 48 MHz Frequency For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz For 4.
PIC18F2458/2553/4458/4553 TABLE 4-1: Param No. Sym A/D CONVERTER CHARACTERISTICS: PIC18F2458/2553/4458/4553 (INDUSTRIAL) PIC18LF2458/2553/4458/4553 (INDUSTRIAL) Characteristic A01 NR Resolution A03 EIL Integral Linearity Error A04 A06 A07 EDL EOFF EGN Differential Linearity Error Offset Error Gain Error A10 — A20 ΔVREF Reference Voltage Range (VREFH – VREFL) Min Typ Max Units Conditions — — 12 bit ΔVREF ≥ 3.0V VDD = 3.0V ΔVREF ≥ 3.0V — ±1 ±2.0 LSB — — ±2.0 LSB VDD = 5.
PIC18F2458/2553/4458/4553 FIGURE 4-3: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 (1) 132 11 A/D DATA 10 9 ... ... 3 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F2458/2553/4458/4553 5.0 PACKAGING INFORMATION For packaging information, see the “PIC18F2455/ 2550/4455/4550 Data Sheet” (DS39632). © 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553 NOTES: DS39887C-page 38 © 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553 APPENDIX A: REVISION HISTORY Revision A (May 2007) Original data sheet for the PIC18F2458/2553/4458/ 4553 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (June 2007) Changes to Figure 4-2: PIC18LF2458/2553/4458/4553 Voltage-Frequency Graph (Industrial). Revision C (October 2009) Removed “Preliminary” marking.
PIC18F2458/2553/4458/4553 APPENDIX C: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F2458/2553/4458/4553 INDEX A M A/D ..................................................................................... 21 A/D Converter Interrupt, Configuring ......................... 25 Acquisition Requirements .......................................... 26 ADCON0 Register ...................................................... 21 ADCON1 Register ...................................................... 21 ADCON2 Register ...................................................... 21 ADRESH Register ......
PIC18F2458/2553/4458/4553 ADCON1 (A/D Control 1) ........................................... 22 ADCON2 (A/D Control 2) ........................................... 23 DEVID1 (Device ID 1) ................................................ 32 DEVID2 (Device ID 2) ................................................ 32 Revision History ................................................................. 39 S Special Features of the CPU ..............................................
PIC18F2458/2553/4458/4553 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F2458/2553/4458/4553 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2458/2553(1), PIC18F4458/4553(1), PIC18F2458/2553T(2), PIC18F4458/4553T(2); VDD range 4.2V to 5.5V PIC18LF2458/2553(1), PIC18LF4458/4553(1), PIC18LF2458/2553T(2), PIC18LF4458/4553T(2); VDD range 2.0V to 5.
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