Datasheet

PIC18F2455/2550/4455/4550

UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 57, 168

UADDR

— ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 57, 173

UCON

— PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 57, 166

USTAT

— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 57, 171

UEIE BTSEE

— — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 57, 185

UEIR BTSEF

— — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 57, 184

UIE

— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 57, 183

UIR

— SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 57, 181

UFRMH

— — — — — FRM10 FRM9 FRM8 ---- -xxx 57, 173

UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 57, 173

SPPCON

(3)

— — — — — — SPPOWN SPPEN ---- --00 57, 191

SPPEPS

(3)

RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 57, 195

SPPCFG

(3)

CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 57, 192

SPPDATA

(3)

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 57, 196

TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Details

on page

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.

Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.

2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.

3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.

5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.

6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

7: I

C™ Slave mode only.