Datasheet

© 2009 Microchip Technology Inc. DS39632E-page 71
PIC18F2455/2550/4455/4550
EEADR EEPROM Address Register 0000 0000 55, 91
EEDATA EEPROM Data Register 0000 0000 55, 91
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 55, 82
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 55, 83
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 56, 109
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 56, 105
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 56, 107
IPR1 SPPIP
(3)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 56, 108
PIR1 SPPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 56, 104
PIE1 SPPIE
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 56, 106
OSCTUNE INTSRC
— — TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 56, 28
TRISE
(3)
— — — — — TRISE2 TRISE1 TRISE0 ---- -111 56, 126
TRISD
(3)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 56, 124
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0 11-- -111 56, 121
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 56, 118
TRISA
— TRISA6
(4)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 56, 115
LATE
(3)
— — — — — LATE2 LATE1 LATE0 ---- -xxx 56, 126
LATD
(3)
LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 56, 124
LATC LATC7 LATC6
— — — LATC2 LATC1 LATC0 xx-- -xxx 56, 121
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 56, 118
LATA
—LATA6
(4)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 56, 115
PORTE RDPU
(3)
— — —RE3
(5)
RE2
(3)
RE1
(3)
RE0
(3)
0--- x000 56, 125
PORTD
(3)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 56, 124
PORTC RC7 RC6 RC5
(6)
RC4
(6)
— RC2 RC1 RC0 xxxx -xxx 56, 121
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 56, 118
PORTA
—RA6
(4)
RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 56, 115
UEP15
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP14
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP13
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP12
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP11
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP10
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP9
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP8
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP7
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP6
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP5
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP4
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP3
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP2
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP1
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I
2
C™ Slave mode only.