Datasheet

© 2009 Microchip Technology Inc. DS39632E-page 389
PIC18F2455/2550/4455/4550
FIGURE 28-6: CLKO AND I/O TIMING
TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 28-4 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)
11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)
12 TckR CLKO Rise Time — 35 100 ns (Note 1)
13 TckF CLKO Fall Time — 35 100 ns (Note 1)
14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 T
CY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO ↑ 0.25 T
CY + 25 — — ns (Note 1)
16 TckH2ioI Port In Hold after CLKO ↑ 0——ns(Note 1)
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to
Port Input Invalid
(I/O in hold time)
PIC18FXXXX 100 — — ns
18A PIC18LFXXXX 200 — — ns V
DD = 2.0V
19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup
time)
0——ns
20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns
20A PIC18LFXXXX — — 60 ns V
DD = 2.0V
21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns
21A PIC18LFXXXX — — 60 ns VDD = 2.0V
22† T
INP INTx pin High or Low Time TCY ——ns
23† T
RBP RB7:RB4 Change INTx High or Low Time TCY ——ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.