Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 308 © 2009 Microchip Technology Inc.
25.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY
TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — —CP3
(1)
CP2 CP1 CP0
300009h CONFIG5H CPD CPB
— — — — — —
30000Ah CONFIG6L
— — — —WRT3
(1)
WRT2 WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — —
30000Ch CONFIG7L
— — — — EBTR3
(1)
EBTR2 EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
24 Kbytes 32 Kbytes
Address
Range
Boot Block Boot Block
000000h
0007FFh
CPB, WRTB, EBTRB
Block 0 Block 0
000800h
001FFFh
CP0, WRT0, EBTR0
Block 1 Block 1
002000h
003FFFh
CP1, WRT1, EBTR1
Block 2 Block 2
004000h
005FFFh
CP2, WRT2, EBTR2
Unimplemented
Read ‘0’s
Block 3
006000h
007FFFh
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
008000h
1FFFFFh
(Unimplemented Memory Space)