Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 298 © 2009 Microchip Technology Inc.
REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 R/P-0 R/P-0 U-0 U-0 R/P-1 U-0 R/P-1
DEBUG
XINST ICPRT
(1)
— —LVP —STVREN
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7 DEBUG
: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5 ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit
(1)
1 = ICPORT enabled
0 = ICPORT disabled
bit 4-3 Unimplemented: Read as ‘0’
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: Available only in the 44-pin TQFP packages. Always leave this bit clear in all other devices.