Datasheet

PIC18F2455/2550/4455/4550

U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0

— — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-6 Unimplemented: Read as ‘0’

bit 5 USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)

1 = USB clock source comes from the 96 MHz PLL divided by 2

0 = USB clock source comes directly from the primary oscillator block with no postscale

bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits

For XT, HS, EC and ECIO Oscillator modes:

11 = Primary oscillator divided by 4 to derive system clock

10 = Primary oscillator divided by 3 to derive system clock

01 = Primary oscillator divided by 2 to derive system clock

00 = Primary oscillator used directly for system clock (no postscaler)

For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:

11 = 96 MHz PLL divided by 6 to derive system clock

10 = 96 MHz PLL divided by 4 to derive system clock

01 = 96 MHz PLL divided by 3 to derive system clock

00 = 96 MHz PLL divided by 2 to derive system clock

bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits

111 = Divide by 12 (48 MHz oscillator input)

110 = Divide by 10 (40 MHz oscillator input)

101 = Divide by 6 (24 MHz oscillator input)

100 = Divide by 5 (20 MHz oscillator input)

011 = Divide by 4 (16 MHz oscillator input)

010 = Divide by 3 (12 MHz oscillator input)

001 = Divide by 2 (8 MHz oscillator input)

000 = No prescale (4 MHz oscillator input drives PLL directly)