Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 292 © 2009 Microchip Technology Inc.
25.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L
— — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN
— — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L
— — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE
— — — — LPT1OSC PBADEN CCP2MX 1--- -011
300006h CONFIG4L DEBUG
XINST ICPRT
(3)
— —LVP—STVREN100- -1-1
300008h CONFIG5L
— — — —CP3
(1)
CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB
— — — — — — 11-- ----
30000Ah CONFIG6L
— — — —WRT3
(1)
WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — — 111- ----
30000Ch CONFIG7L
— — — —EBTR3
(1)
EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H
—EBTRB— — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx
(2)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010
(2)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
2: See Register 25-13 and Register 25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by
the user.
3: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.