Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 24 © 2009 Microchip Technology Inc.
FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM
PIC18F2455/2550/4455/4550
FOSC3:FOSC0
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
XT, HS, EC, ECIO
T1OSC
CPU
Peripherals
IDLEN
INTOSC Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
Clock
Control
OSCCON<1:0>
Source
8 MHz
31 kHz (INTRC)
0
1
OSCTUNE<7>
and Two-Speed Start-up
96 MHz
PLL
PLLDIV
CPUDIV
0
1
0
1
÷ 2
PLL Prescaler
MUX
111
110
101
100
011
010
001
000
÷ 1
÷ 2
÷ 3
÷ 4
÷ 5
÷ 6
÷ 10
÷ 12
11
10
01
00
PLL Postscaler
÷ 2
÷ 3
÷ 4
÷ 6
USB
USBDIV
FOSC3:FOSC0
HSPLL, ECPLL,
11
10
01
00
Oscillator Postscaler
÷ 1
÷ 2
÷ 3
÷ 4
CPUDIV
1
0
Peripheral
FSEN
÷ 4
USB Clock Source
XTPLL, ECPIO
Primary
Clock
(4 MHz Input Only)