Datasheet

© 2009 Microchip Technology Inc. DS39632E-page 257
PIC18F2455/2550/4455/4550
FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM
FIGURE 20-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED)
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1
SPPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1
SPPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
RCREG EUSART Receive Register 55
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
x64 Baud Rate CLK
Baud Rate Generator
RX
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR FERR
RSR Register
MSb
LSb
RX9D RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop
Start
(8) 7 1 0
RX9
• • •
SPBRGSPBRGH
BRG16
or
÷ 4
RXDTP
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0
Stop
bit
Start
bit
Start
bitbit 7/8
Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.